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Published: Friday, 02 July 2021 12:19
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DRAM Memory

When we talk about volatile memory, almost always we talk about DRAM (more specifically SDRAM). Wikipedia: https://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory

Good article on basics of DRAM (taken from NXP): nxp_ddr_dram_basics

A DRAM memory module that you buy from market (long stick like with pins on one side) is a DIMM. It has multiple memory chips on it (usually 8 or 9). These are the actual memory chips that have the memory array in them. Each chip supplies 8 bits (or 16 bits in newer ones) of the DRAM bus. So, these 8 or 9 chips supply 64 or 72 bits (or 128 bits or more on newer ones) of the whole data bus.

Various gen of SDRAM:

1. SDR (or SDR SDRAM): This is the single data rate SDRAM. "SDRAM" term is also sometimes used for single data rate DRAM. However, SDRAM is usually meant for Synchronous DRAM. So, we should instead use "SDR SDRAM" for single data rate SDRAM. This was the 1st generation of DRAM which output data once every clock cycle (i.e data sent or received on only rising or falling edge). Clock speeds were from 66MHz to 133MHz. Supply Voltage was 3.3V.

2. DDR (or DDR SDRAM): This is the double data rate SDRAM. To double up the speed without increasing the clock speed, DDR SDRAM were introduced, which allowed data change to happen twice every clock cycle = once on rising edge and once on falling edge. This effectively doubled the bandwidth, as we would get the double the data rate even with the same clock speed.

JEDEC standard for naming memory chips:

So, specifying clock speed for memory chips wouldn't make sense, as that would imply that DDR memory have same speed as SDR memory (or they have the same bandwidth). So, JEDEC came up with a standard, which allowed effective speeds or bandwidth to be specified.

  • Speed convention: This specifies effective clock speed of memory module and has prefix as SDR/DDR followed by effective clock speed. It is of the form SDRxxxx or DDRxxxx where xxx refers to the effective clock speed of the memory stick. So, SDR mem with 200MHz was named SDR-200, while DDR mem with 200MHz was named DDR-400 (as 200MHz clk speed for DDR mem is effectively 400MHz clk speed as both rise/fall edges used). We also use nomenclature as DDR2-800 to further clarify that it's DDR2 memory.
  • Bandwidth convention: This specifies effective bandwidth (bytes/sec) of memory module and has PC as prefix followed by bandwidth in MB/sec. Memory chips were identified as PCxxxx where xxx refers to the effective bandwidth (in MB/Sec) of the memory stick. So, DDR2-800 memory stick which has 64 bit data interface is transferring 8bytes*800MHz = 6400MB/sec. So, it's named PC6400 or PC2-6400.

DDR Generations:

Various generation of DDR were introduced starting from year 2000. Below are the 5 gen of DDR memory as of 2020. None of the DDR mem are backwards compatible with SDR mem as the supply voltage was reduced from 3.3V which was the supply voltage of SDR mem. 

  • DDR1: Here, clock speeds were 133MHz to 200MHz. However, since data was rd/wrt twice every cycle, effective clock speed was 266MHz to 400MHz. Supply voltage was 2.5 V. For a 133MHZ SDR to be converted to DDR, clock rate of internal RAM operations wasn't changed. Instead, internally in SDRAM, 2 databits were pumped out on every +ve edge of clock cycle. This was done by allowing 2 parts of mem array to dump out the 2 bits in parallel. These were put in a 2 bit prefetch queue. Externally, the data bus grabbed bits from this prefetch queue 2 times every cycle, one on rising edge of clk, and other on falling edge of clk.
    • Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400. Corresponding 184-pin DIMMs (having 64 bit or 8 byte data i/f) are known as PC-2100, PC-2700 and PC-3200. DDR-550 also available.
  • DDR2: DDR2 SDRAM is very similar to DDR1 SDRAM, but doubles the minimum read or write unit again, to four consecutive words. It does this by doubling the bus rate of the SDRAM without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. The prefetch queue depth was doubled from 2 bits to 4 bits deep, so that internal memory can dump 4 bits of data every cycle (due to doubling of width of memory). So, from external memory i/f, 2 bits can be transferred with every cycle (one on rising edge and one on falling edge). Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips. Supply voltage was 1.8 V. 
    • Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800. Corresponding 240-pin DIMMs (still has 8 byte data i/f) are known as PC2-3200 through PC2-6400. DDR2-1066 and DDR2-1250 also available.
  • DDR3: DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words (prefetch queue depth of 8). This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. Supply voltage was reduced to 1.5 V. DDR3 was mass adopted around 2008. DDR3 allowed max memory of 16GB per DIMM. DDR3 also has low voltage version called DDR3L which operates at 1.35V.
    • Typical DDR3 SDRAM clock rates are 400, 533, 666 or 800 MHz, generally described as DDR3-800, DDR3-1066, DDR3-1333 and DDR3-1600. Corresponding DIMMs (still has 8 byte data i/f) are known as PC3-6400 through PC3-12800. DDR3-2800 also available.
  • DDR4: DDR4 improves speeds further, but NOT by increasing the prefetch depth. Depth is still kept at 8, but banks are divided into more selectable bank groups where transfers to different bank groups may be done more rapidly. Internal banks are increased to 16 (4 bank select bits), with up to 8 ranks per DIMM. Supply voltage VDD/VDDQ was reduced to 1.2 V, with a 2.5 V auxiliary supply for wordline boost called VPP. DDR4 was introduced in 2014 and is still the most widely used memory as of 2022. DDR4 allowed max memory of 64GB per DIMM. DDR4 has NO low voltage version. DDR4 memory is supplied in 288-pin DIMMs, similar in size to 240-pin DDR3 DIMMs, by placing the pins more closely (0.85mm vs 1mm).
    • Typical DDR4 SDRAM clock rates are 800 to 1600 MHz, generally described as DDR4-1600 to DDR4-3200. DDR4-4800 also available.
  • DDR5: DDR5 is a major departure from previous gen mem, where it has active circuitry on the DIMM, which makes interface to the DIMM different from the interface to the RAM chips themselves. DDR5 DIMMs are supplied with management interface power at 3.3 V, and use on-board circuitry and associated passive components to convert to the lower voltage required by the memory chips. Final voltage regulation close to the point of use provides more stable power. Spec was released in 2020, and has yet to get mass adoption (a of 2022). Max DIMM capcity is 512GB.
    • Typical DDR5 SDRAM clock rates are 2400 MHz, generally described as DDR5-4800. It's quite a feat that we have clks running at 2.4GHz on PCB traces connecting 2 chips. Earlier, such Multi GHz clks could only run inside a chip generated locally from PLL.

 

Low Power DDR (LPDDR):

What we talked above was regular DDR mem used in laptops and desktops. LPDDR is a variant of DDR that consumes less power and is targeted for laptops, tablets and mobile phones. LPDDR technology standards are developed independently of DDR standards. LPDDR allows 16 and 32 bit data i/f in addition to 64 biit dat i/f that is std in regular DDR mem modules. Their mem capacity is smaller than their desktop cuounter parts as they are smaller in form factor.

  • LPDDR1: This is a slightly modified form of DDR1 to reduce power consumption. Power supply is reduced from 2.5V to 1.8V. LPDDR1 only had one voltage for all circuits (VDD) at 1.8 V. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Additionally, chips are smaller, using less board space than their non-mobile equivalents.
  • LPDDR2: Similar to previous low power version, but more power efficient than DDR2. LPDDR2 created a separate voltage for the data bus (VDDQ), the command/address bus (VDDCA) and peripheral circuits (VDD2) at 1.2 V, keeping VDD (which powered the main memory array), now renamed to VDD1 at 1.8 V. We refer to operating voltage of LPDDR2 as 1.2V, even though the main interbal capcitive memory runs at 1.8V.
  • LPDDR3: LPDDR3 offers a higher data rate, greater bandwidth and power efficiency, and higher memory density. It went mainstream in 2013, running at 800 MHz DDR (1600 MT/s). At 64 bit data i/f, it implies 1600*8=12800MB/sec which is comparable to notebook memory from 2011. Samsung introduced the first 4Gbit 20nm DDR3 module capable of transmitting 2133MT/s. Supply voltages of LPDDR3 were same as those of LPDDR2.
  • LPDDR4: Doubling of i/f speed to 1600MHz (3200MT/s), and consuming 50% less energy. This was achieved partially by lowering VDDQ/VDD2 slightly to 1.1V, (from 1.2V)  removing VDDCA, but still keeping VDD1 at 1.8V. Hence we refer to operating voltage of LPDDR4 as 1.1V.
  • LPDDR5: Spec for LPDDR5 was published in 2019. It doubled the speed to 6400MT/s, and used differential clocking. It has bunch of power saving techniques. LPDDR5 created two possible values for VDD2, 0.9 V (low) or 1.05 V (high), depending on the frequency the memory is running, also allowing VDDQ to be between 0.3 V and 0.5 V. VDD1 was kept same as previous gens at 1.8V.

 

Graphics DDR (GDDR):

We talked about DDR mem above which are used mainly for cpu, but we also have DDR mem designed specifically for GPU, which require much higher bandwidth. These are called GDDR, and you see this mentioned on computers, which have a dicrete graphics card. Just like regular DDR gen, we have GDD1, GDDR2, etc. Transfer rate for GDR5 is about 100GB/sec.

 

DDR Memory interface and Commands:

The bus that connects the memory pins on microprocessor to the pins on the memory chip (DIMM on the motherboard) is known as the memory bus interface. There are bunch of cmds that are driven on these pins that dictate the operation.

There are 2 good articles on "Introduction to DRAM operation":

Intro to DRAM => https://www.allaboutcircuits.com/technical-articles/introduction-to-dram-dynamic-random-access-memory/

Basic operation => https://www.allaboutcircuits.com/technical-articles/executing-commands-memory-dram-commands/

Let's look at organization of DRAM memory chips and the DIMM:

DIMM: Contains multiple onboard DRAM chips. DIMM will have the memory size of DIMM as well as the organization detail as 2Rx8 etc.

  • DIMM module organization:
    • Rank: The rank of a DRAM module is the highest level of organization within a DIMM. A rank is a separately addressable set of DRAMs within a DIMM. In earlier chips, all DRAM chips on a DIMM would be addressed by a given addr. This was because each DRAM chips provided some bits of the final data bus that was output from the DIMM. In case of DIMM with 64 bit data bus o/p, 8 DRAM chips each 8 bit wide would provide 64 bits. So, Rank of chip was 1. However, later with memory capacity increasing and more and more DRAM chips on a single DIMM, we could separate out the DRAM chips into groups, where each group behaved like a single DIMM. One group has no relation to other group. So, ranks can be considered to be like different DIMM, except that they are physically on a single board.
  • DRAM chip organization:
    • Bank: Bank is the next level of organization below a rank. Bank is organization of memory arrays within a DRAM chip. So, while Rank refers to organization at DIMM level, banks refers to organization at DRAM chip level. Each bank operates independently of the others. This means that reading, writing, and precharging can all be done on one bank without impacting the other. Each bank may have multiple memory arrays, where each array is a set of rows and columns of memory. Each memory array outputs 1 bit, so the size of the output width of a bank indicates the number of arrays it has. Therefore in a x4 DRAM chip, the internal banks would each have four memory arrays. Only 1 bank is accessed at a time in each dram chip, so banks can be thought of as ranks within a DRAM chip.
      • NOTE: Multiple Banks may also be combined to form a Bank Group.
    • Rows/Columns: Banks are further divided into rows and columns, which are grouped into memory arrays. Each memory array outputs 1 bit as explained above.

 

DRAM Chip Interface:

Though pins for DRAM chips vary a little from gen to gen and among different vendors, there are few pins that are fundamental to operation of DRAM. Most of these pins are provided as differential signal (i.e complimentary signals in pair) as that provides btter noise immunity. Major pins of DRAM are:

  • Clock: This is the main clock provided as i/p to the DRAM chip.
    • CMD/ADDR CLK CK (Differential clock signal, i/p): This is pair of clock signals sent to the DRAM chip that is used to sample all the i/p signals for control and Addr (NOT to latch data signals) as shown below. This is differential (i.e +ve and -ve clk) so that it has better noise immunity. Historically clk has always been provided as differential pair, as clk needs to be very clean and free of glitches, else wrong values may get captured. Cmd/Addr are sampled on both edges of clk, so this is ddr clk. Cmd/Addr signals are lower speed, so this clk is usually slower than dataclk discussed later.
    • Clock Enable CKE => Some early generation of chips had a separate clock en pin, which would enable clk when when this pin was high. CKE was pulled low for auto/self refresh cmd as those cmds didn't need a clk.
    • WRT DATA CLK WCK (Differential clock signal, i/p): This is pair of clock signals sent to the DRAM chip for Write data capture and Read data output. CMD/ADDR clk is a separate clk (discussed above) that can't be used as wrt data clk, as wrt data clk is 2X-4X faster to support higher freq writes. This clk is also used for outputting read data and read strobe signal from the DRAM chip back to SOC. Wrt data is centered b/w the rise and fall edge of wrt clk.
  • Control/Addr: These are control signals that determine the action to take.
    • Chip Select CS# (active low i/p) => This activates the selected DRAM chip when low. All other DRAM chips with CS# high are not activated. At the DIMM level, there is a bus of CS#[x:0] coming in, which goes thru a decoder, and that decides which DRAM chip to select. This is sampled on rising edge of Cmd/Addr clk.
    • Cmd/Addr CA[x:0] (i/p bus) => This is a bus that serves dual purpose. It has cmd phase and Addr phase. Various cmds such as read, write, precharge, etc are sent on cmd bus, followed by the Addr to which this cmd applies to. This is the most common approach on latest gen of DDR, though earlier chips had many more pins to achieve the same purpose. Some of these are listed below:
      • Bank Addr BA[x:0] => Since we may have multiple banks, there is a separate bank addr too on some of the chips. Bank Addr bus may be considered part of the same Addr bus, as it's functionally just one big set of addr.
      • Row/Col addr strobe RAS#/CAS# (active low i/p)=> For Addr, we didn't separate out row/col addr. Both of them are embedded into the Addr bus. Row and col addr are provided in 2 separate cycles. The cmd protocol itself may define which is col addr and which is row addr. In many chips, we have dedicated pins called RAS# (Row addr strobe) and CAS# (column addr strobe) which indicate when row addr is going on the Addr bus and when col addr is flowing on Addr bus. Both RAS# and CAS# are active low.
      • Write Enable WE# (active low i/p) => We need a separate line for saying whether it's read or wrt. When low, it indicates a Rd cmd, while high indicates a wrt cmd. RAS, CAS and WE together define a cmd. Now these are all embedded within CA[x:0] bus.
  • Data: This refers to Data signals to Rd or Write. There's also a strobe signal that goes with this data bus, that serves as the clk for the data signals
    • Data DQ[x:0] (bidirectional bus) => This is Data bus that carries the data to be written to memory (in case of write cmd) or data read from memory (in case of read cmd). Optional ECC (Error correcting Code) bits are also provided on few of these lines to help with Error correction. This bus is bidirectional.
    • Data Strobe DQS[x:0] (bidirectional bus) => This is the strobe signal for Data bus. Since clk is already provided to the DRAM chip as i/p to latch all incoming signals, the same clk may be used as the clk for latching the rd/wrt data. The problem is that clk may be shifted and not perfectly aligned. So, a separate strobe for rd/wrt is needed. Write data and strobe are both driven by same clk on SOC (system on chip) chip, but are aligned with help of a DLL (Delay lock loop). This data strobe is used to latch wrt data on the DRAM chip. However, if we have separate clk lines for wrt (Wrt Data Clk), then we don't need strobe for write, in which case, this strobe signal is only used for Rd. For read, we do the same thing as wrt. Rd data and strobe are both driven by same clk (wrt clk) on DRAM chip, but are aligned with help of a DLL (Delay lock loop). This data strobe is used to latch rd data on the SOC chip. For this reason, DQS is bidirectional. DQS is edge aligned with read data, but centered in wrt data.
    • Data Mask DM[x:0] => These are data mask bits that can be used to mask data bytes that we don't want to write to DRAM chip. Since DM bits are similar to Wrt Data bits, they are also latched using Data strobe. Mask bits are usually on per byte basis. These Mask bits may also have other function, when wrt is not taking place.
  • Power: This refers to power supply and gnd signals.
    • VDDQ/VSSQ => These are the power supply for o/p ports of the DRAM chip. i/p ports will also need this power supply for the level shifter before the signal gets into the internal power domain. DRAM IO power follows the level of VDDQ input.
    • VDD/VSS => These are to power everything else except the IO ports. All internal circuitry, peripheral logic, DRAM memory, etc is running of this supply. These were subdivided into 2 parts after few gen to save power:
      • VDD1 => This is the main power that powers the capacitive memory array. The voltage here is usually the highest. Most critical voltage as memory array rd/wrt speed dependent on this voltage.
      • VDD2 => This is the peripheral power which powers all logic which are not on IO and not in capacitive memory array. This is kept lower than VDD1 to save on power. It can be lowered even further depending on Freq requirement of the DRAM.
    • VREF => This is a reference voltage provided as input.

 

DRAM Basic cmds:

Though there are many cmds in the latest gen of DRAM chips, these are few basic cmds that are needed for all DRAM chips. In chips, which have separate cmd pins, combo of CAS, RAS, We and CKE determine what cmd is going to be executed. In newer gen chips, this cmd is embedded within the cmd bus, as there are no separate cmd pins. Below are the 5 basic cmds for any rd or wrt to take place. We start with Activate phase, followed by precharge, then a rd/wrt takes place. Auto Refresh happens in parallel every so often to preserve DRAM values.

  • Activate (row access): Activate is essentially the row access command. Meaning, it opens up a row and moves the charge from the capacitors into the sense amplifiers. Accessing a row is always done before a column in DRAM. This command is paired with inputs to a bank address register (that selects the current bank) and a row address register (that selects the desired row). One important note on the activate command is that whichever row is currently open remains open until a precharge command is issued (more on precharge later). To use this command most DRAMs require CS and RAS to be pulled low, while CAS and WE are pulled high.
  • Precharge (row precharge): Precharge deactivates the row currently open in a bank. When issued a precharge command, the DRAM is told to restore the values read from the row of capacitors. This is done by the sense amplifiers and when completed prepares the bank for another row access. Precharge is performed by pulling CS, RAS, and WE low and leaving CAS high.
  • Read (col access): The read command can also be thought of as a column read command. When combined with a proper bank address and column address, the data recently moved into the sense amplifiers from an activate command (row access) is now pushed onto the data bus. DRAMs often include a “Read and Auto-Precharge” command that performs the column read and then closes/precharges the row. This way, a separate precharge command need not be issued. If the same row, but a different column, needed to be accessed then a precharge would not be issued at all and the row would be left open. To use the read command CS and CAS are pulled low, while RAS and WE are pulled high. 
  • Write (col access): A write command is virtually the same as a read, except for the direction of the data. During a write command, data is pulled off of the data bus and put into the selected bank, row, and column. Auto-precharging can be performed much like a read and closes the currently activated row when the write is done. To perform a write, CS, CAS, and WE are pulled low, while RAS is held high.
  • Auto Refresh: In DRAM, the refresh command is issued every so often. It's needed since DRAM bits loses charge over time (irrespective of whether it's accessed or not). All bits will need to be refreshed every so often. One important aspect of refreshing is that any active banks should be precharged before the command is issued. To perform a refresh CS, RAS, and CAS are pulled low with WE high. After refreshing, the DRAM keeps track of the last refreshed row and increments a refresh counter so that the next refresh command will operate on the next row. When a refresh command is issued, the current row in every bank is refreshed. Most DRAMs will perform 8192 refresh cycles every 64 ms. That's every 7.813 μs. This has remained constant despite growing device densities. 
  • Other Cmds: Other common DRAM commands include NOP (No Operation), Burst Terminate, and Load Mode Register. NOP is used to force the DRAM to do nothing. This is useful when the DRAM needs to wait, for instance if it is currently being refreshed. In reality, read and writes to DRAM are done in short bursts. Burst terminate will truncate the read or write command, i.e., stop it prior to finishing. DRAM can be placed into different modes. These modes are changed via the Load Mode Register command.

 

LPDDR5:

 We'll look at LPDDR5 Memory i/f from JEDEC spec: (JEDEC spec is only available to members, but I'll list imp stuff below):

 

 

 

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Published: Friday, 25 June 2021 18:55
Hits: 1059

Selected websites for practice:

A lot of websites advertise "free sample papers" for practicing, but soon you realize that these are for profit websites, and want your money. You should not have to pay for any educational resource in today's internet era. So, I've compiled a list below of free practice papers. I've listed papers starting from Elementary School to High School. Advanced Maths papers beyond High School will be in their respective sections.

1. STAAR tests: In Texas, students have to pass STAAR test in order to move to next grade. These question papers are available for free here, so that you can see the complexity of questions expected. Look for Maths papers from Grade 3 to High School:

https://tea.texas.gov/student-assessment/testing/staar/staar-released-test-questions

2. math-only-math website: This website is mentioned under maths section: https://www.math-only-math.com/. This has lots of sample questions for each grade and for each topic. I don't think you can find more comprehensive material than this for practicing.

3. Math10 website: Math10 has questions for each grade and each topic, separated out under easy, medium and hard. Link => https://www.math10.com/problems/

4. mathoplis website: This website is mentioned under maths section: https://www.mathopolis.com/questions/skills.php and https://www.mathopolis.com/questions/quizzes.php

5. Khan Academy: Last, but the best. It not only has teaching videos, but tons of practise material for all grades. There is course challenge for each subject in each grade, that you find once you go that grade and that subject. One such example for 8th grade maths is here:

https://www.khanacademy.org/math/8th-grade-illustrative-math#8th-grade-illustrative-math-subject-challenge

On each topic of each subject, there is a separate quiz, and mastery questions, which are very helpful. Each lesson is accompanied by "practice questions" and a "quiz". This helps you as you watch videos and solve these questions.

6. byjus website: CBSE (India) sample papers for 8th grade: The questions are harder compared to 8th grade in USA. Link => https://byjus.com/cbse-sample-papers-for-class-8-maths/

 

Sample papers for practice:

Few other sample maths papers picked from internet. I've provided a link, as well as downloaded the document to my server, and provided a link. That way, if the online document disappears (as it happens quite frequently)

A. Baschools:

8th grade: Downloaded from here: https://www.baschools.org/pages/uploaded_files/Pre-Algebra%20Practice%20Test.pdf  => Local copy => Maths-8th-grade-Pre-Algebra-Practice-Test.pdf

B. ne.gov: (nebraska state)

8th grade: Download from here: https://www.education.ne.gov/wp-content/uploads/2017/07/NEG8MathPTPaper.12.06.10.pdf => Local copy => NEG8MathPTPaper120610.pdf

C.Louisiana believes: This is one of the highest quality maths papers that you can find anywhere. If the kid can solve almost all questions here, he's good for that grade:

All Sample papers from 3rd grade to 8th grade are provided here: https://louisianabelieves.com/resources/library/practice-tests

The link above does have sample papers, but hard to navigate. So, I provided pdf links separately for some of the maths ones.

5th grade: Download from here: http://www.stjames.k12.la.us/common/pages/displayfile.aspx?itemid=12921575

6th grade: Download from here: https://louisianabelieves.com/docs/default-source/assessment/leap-connect-grade-6-math-practice-test-reference-materials.pdf?sfvrsn=fc32991f_2

7th grade: Download from here: http://www.stjames.k12.la.us/common/pages/displayfile.aspx?itemid=12921698

 8th grade: Download from here: https://www.louisianabelieves.com/docs/assessment/practice-test-math-grade-8.pdf => Local copy => practice-test-math-grade-8.pdf

D. everestva: Lots of sample papers here (both US as well as papers from India too)

https://everestva.com/search/grade-8-maths-exam-papers-and-answers-pdf

Some sample papers from above website:

1. Nebraska state, USA: Need one paper: FIXME ..

2.Australia, Kinross college: Download from here: https://kinrosscollege.wa.edu.au/wp-content/uploads/2017/11/Year-8-Maths-Exam-Sem-2-2016.pdf

=> Local copy => Year-8-Maths-Exam-Sem-2-2016.pdf

3. south africa (zambia): Download from here: https://www.education.gov.za/Portals/0/CD/Curriculum%20doc%20question%20Papers2007/2015%20ANA%20Gr%208%20Mathematics%20Test%20-%202015.pdf?ver=2015-08-05-213322-000

=> Local copy => 2015_ANA_Gr_8_Mathematics_Test_-_2015.pdf

4. namibia (grade 8 + grade 9): Download from here: http://www.nied.edu.na/assets/documents/02Syllabuses/04JuniorSecondary/Mathematics/JS_Math_Specimen_Papers1_and_2_March_2018.pdf

=> Local copy => JS_Math_Specimen_Papers1_and_2_March_2018.pdf

5. zambia:  Download from here:   https://www.mathsatsharp.co.za/wp-content/uploads/2015/10/November_Exam_2015_Grade_8.pdf

=> Local copy => November_Exam_2015_Grade_8.pdf

6. Australia (Acara): Bunch of papers from past couple years. Choose "numeracy" for maths papers. Year 9 might be for 8th grade students, though questions look simple. Link to download all the papers: https://www.acara.edu.au/assessment/naplan/naplan-2012-2016-test-papers

E. UK School papers: Few sample papers which look to be at Middle school level:

https://examberrypapers.co.uk/resources/free-11-plus-practice-papers/maths/

 

 

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Published: Monday, 03 May 2021 17:22
Hits: 4085

Landscaping:

if you buy a standalone house, chances are high that it will have a lawn in the front and in the back. If you are buying a condo, lawn care is taken care of by the HOA (Home owner Association). If you are buying a townhome, you may have to take care of the small lawn (if any), depending on the specific HOA.

Lawn care requires considerable time and money. If you are buying a brand new house, it will come with the lawn setup with grass and small plants and trees. You will immediately see 2 kind of areas: one with grass, while the other with no grass, but having cut wood (known as mulch). This mulch area is around trees and plants, so that no grass grows in that area. It's just to give a better appearance to the lawn.

If you buy a house in USA which is part of an association, then one of the long lasting nightmares as a homeowner are the landscaping violations. The whole and sole reason HOA  exist is to make sure that can fine home owners if they don't like the landscaping of that particular home. This is easy and recurring money stream for the management company which manages the HOA (as half of the fines go to mgmt Co). All other fines are very objective, can be contested easily and are one time fix. On the other hand, landscaping rules are very obscure (something like "landscaping has to be maintained in a first class condition"), can be sent out weekly, and for any reason (weeds in yard, grass on mulch, dead plants after winter, not enough green color to grass, blah blah, basically anything you can dream of ...)

No matter how much you maintain your yard, management company will always find a way to send you a violation notice. They will start imposing fines, interest, etc, and there is little respite from this. In the past, HOAs have spent hundreds of thousands of dollars filing lawsuits over landscaping, and have successfully foreclosed homes, which is totally illegal and non sense. Many HOA just fine you when they come to know that you haven't hired a professional to maintain your yard. Best thing is to avoid buying a home in an HOA. However no new homes in USA come without an HOA, so you are stuck.

Maintaining landscaping is one thing, and not getting fines is another thing. You can spend a lot of money and time trying to avoid HOA fines related to landscaping. I don't know when will that suffice. My article below lists general tips and tricks to maintain your landscaping in a decent condition. This will save you money, and require as little of your time as possible.

 My goal is to never spend more than $1K/year on landscaping including all the costs as irrigation, mowing, yard supplies, machines, etc.

 

 

Mowing: 

The very first thing that you will need to do is mow the lawn. This means cutting the grass, preferably every 2 weeks during summer and every 4 weeks during winter. I personally felt that mowing it every week, keeps it much healthier and it takes less time to do it. Regular mowing creates a tillering effect, keeping your grass greener and softer. You will need to buy a lawn mower to do this.

There are 3 different kind of lawn mowers to do this job:

  1. Manual mowers: These require manual effort, as the cutting blades rotate as you move the mower. It's the cheapest option, but takes lot of your energy. Good to exercise, but I don't see these anymore.
  2. Gas mowers: These run on petrol, and maintainance is required on regular basis. Cost in the range of $100-$200.
  3. Electric mowers: These mowers are the most convenient, as they run on electricity. Two options are available here: one with electric cords (corded), and ones without (cordless). Cordless ones have rechargeable battery, so they are heavier than corded ones. But advantage is that there is no cord to buy, and no cord to maneouver around. However, cordless mowers will last for an hour or so in one charge, depending on the battery life, so your lawn has to be less than 10,000 sq ft, or else it's going to require multiple charging in order to complete one mowing. Price wise corded mowers are cheaper than cordless ones. However, if you shop around, you can find cordless mowers for under $300 with good 2 year warranty. Do NOT buy a corded mower as those are difficult to manage, regularly gets the cord cut, and eventually don't end up saving any money. Buy the cordless one. 

Mower deals:

Tips for mowing:

  1. Always leave 3 inches of grass height in the lawn. you can do this by adjusting the height of the mower to 3 inches. Reason for leaving 3 inches is this: grass has 2 parts, a bottom dry part, and the top crown. you don't want to cut bottom dry part.
  2. Never cut more than 1/3rd of the grass height in one mowing. If you've to cut more than this, waiT for 2-3 days, and then again cut, 1/3rd of remaining grass height. this way, grass is healthier.

Mowing is just one lawn care activity. It doesn't prevent the unwanted plants (weeds) from growing. These weeds will grow along with your grass, and start killing your grass, as they take away the necessary resources (water, sunlight) from the grass for their own growth. For these, we need fertilizers and chemical spray. This is covered under next section.

 

 

Weed Control:

Weed Control is best done before weeds grow. Crabgrass is the most common weed that is hard to pull out, and grows very fast. Below are few chemicals that help prevent crabgrass as well as other weeds.

Crabgrass Control (Weeds): https://www.lowes.com/pd/Scotts-32-04-lb-Crabgrass-Control/1000140423

Pre Emergent: These are chemicals that you spray before the weeds come, i.e when weeds are dormant. This is usually in the fall (i.e Nov-Feb). If you spray pre emergent during the fall, you will hardly see any weeds during the summer. If you forget to do this, then it's very hard to control the weeds with post emergents or other chemicals. It's too late by the time you start seeing weeds germinate.

Crabgrass pre-emergent: Crabgrass is pretty easy to control. You just have to put the right chemical/weed killer, else it's impossible to get rid of it. Regular weed killer will work on all other weeds, but will never work on Crabgrass. A chemical, Prodiamine, is very effective. Here's a link: https://www.amazon.com/Quali-Pro-Prodiamine-Pre-Emergent-Herbicide-Granules/dp/B004GTQBEK

Prodiamine Preemergent => It's expensive at $100, however it will last you 10 years or more. Don't buy smaller bottles, as they cost you way more over the long run. This is the way to apply it:

  1. Measure your yard area. Per 1000 sq ft, you need 0.5oz of Prodiamine. The dosage of prodiamine determines how long the yard is going to be crabgrass free. For 4-6 months protection, 0.5 oz is good. For 12 month protection, you need 1 oz per 1000 sq ft. Don't go over 1oz per 1000 sq ft, as that may damage the grass.
  2. Fill in 1 gallon water in the spray tank. 1 gallon is for 2000 sq ft of yard area. Put in 1oz  - 2oz of Prodiamine in it. Shake it well. This amount in spray tank is good enough for 2000 sq ft of yard area. For 4000 sq ft of yard area, repeat twice.
  3. Once the water and the Prodiamine are mixed in the tank, start walking over the yard, spraying it. Within 14 days, turn on your sprinkler system to let this chemical get into your soil. This will have more effective control of weeds.

 Post Emergent: These are chemicals that you spray after the weeds come, i.e when weeds are visible. Most of the weed n feed fertilizers, weed killers, etc you see in the market are the post emergent. These are not as effective as Pre emergents. You need to apply post emergent in conjunction with Pre emergent to get best results. If you have done a good job applying Pre-emergents, you won't need much of post emergents,

 

Grubs: If you see your grass not needing a cut even during active growing season of summer, that means the grass isn't growing, which indicates something wrong with the grass. Most of the times, you will also see that the grass is really easy to pull off from certain places (sometimes it comes out like a carpet indicating no roots at all). The most common reason for this is over abundance of grubs in your soil, which are little worms in soil, which feed on root of any plant including grass. If you are seeing the damage, it's too late as larva of Grubshave already hatched into adults and will keep eating grass. You can control further damage by killing whatever grubs you have by using this 24 hr Grub Killer product => https://www.amazon.com/BioAdvanced/dp/B001H1GQ54

For next season, you should apply grub killer to prevent grubs from laying eggs. This is done in Spring season before summer comes (i.e March/April). So, we kill Grubs before they lay eggs. You need to water extensively to let this chemical go underneath deep in the soil to get all grubs. You need to apply only once a year, as after summer, no grubs will come anyway. You need season long Grub control for this => https://www.amazon.com/Scotts-GrubEx1-Season-Long-Killer/dp/B0050DV4ZW/145-1063152-0610042

 

 

Sprinkler Installation and Repair:

If you have a sprinkler system to water your lawn, it's another financial pain. However, you should be able to do almost every repair yourself, instead of spending 100's of $ for each call. They don't involve any plumbing or fixing difficult leaks, as most of the parts are standard, and may just be switched with a new one. Repairing sprinklers is NOT plumbing job, small leaks here and there may still be OK and NOT that difficult to fix :)

If you dont't have a sprinkler system (especially for old houses), I would suggest to not put one, as it not only saves money, but there's also nothing to maintain. Just use a regular garden hose to water your yard from time to time. Grass may die in extreme summer, but will come back when the weather cools. Just don't allow grass to die to a point where roots start dying. Then, grass won't grow again. Water the lawn before that starts happening. 

First, let's understand the basics of how sprinker system works:

Link showing mock setup=> https://www.youtube.com/watch?v=vYV7Oac5T98

Link showing installation from scratch => https://www.youtube.com/watch?v=GMsVext_DnY

Pipe size:

There is a pvc pipe running under your yard soil, that carries water to all sprinkler head. Pipes are classified based on internal diameter of the pipe. External diameter doesn't matter for fittings. Most of the pipes used in homes are either 1/2 inch pipes or 3/4 inch pipes in internal diameter. The next size up is 1 inch pipe which are mostly used in industrial agriculture, but not in residential yards. You have to know your pipe size.

You have a solenoid, as well as water heads that may go wrong. Lastly, you may have the sprinkler board

Changing Sprinkler heads:

One of the easiest things to do is changing sprinkler heads, They my break, leak, or just not work efficiently after a couple of years. Very easy to replace and each head costs only $5-$10 depending on whether's it's stationary (where head doesn't rotate) or rotary (where head rotates in an angle, and angle is adjustable).

Video explaining how to change heads: https://www.youtube.com/watch?v=c6BDhysSi3A

 

Repair Pipe cuts:

Sprinkler pipes may get cracks,leak or may just accidently get cut while you are diffing in the yard. It's very easy to fix. Tough part is finding out where the leak is. Since it's under the yard, there are multiple ways to find the leak. One is to turn off all faucets, taps in your house, and see if your water meter needle is still moving. That may indicate a leak in the main line before it enters the sprinkler. Sprinkler pipe leaks may not be caught using this process as sprinkler is turned off by the sprinkler board.

To find sprinkler pipe leaks, turn on the sprinkler in manual mode, and check for low water pressure (i.e if not all sprinkler heads come up, that may be a problem with sprinkler head, solenoid or some leak in the pvc pipe for that zone). Rule out the sprinkler head problem by replacing the heads not popping up with new ones. If they still don't pop up, replace the solenoid, and if still doesn't pop up, then chances are there is a leak. Look for water pooling in any certain area, or grass being overly green in same patch of ground. That indicates that patch of grass is getting lot more water underground which can only happen with underground leak.

Once you have dug up, and found the cracked pipe, there are 2 ways to fix it:

 

 

Misc supplies/tools:

Water hose:

You will most likely need a hose to water your grass or your plants at some point. May be because sprinkler stops working, or you might just want to water your grass  little extra. 100 ft hoses with lifetime warranty are available for $50. Buy these. Do NOT buy the "expandable hoses" as they are not going to last beyond one year. They are fancy but that's all they have.

05/25/2025 : 100 ft garden hose => https://slickdeals.net/f/18331678-flexzilla-garden-hose-5-8-in-x-100-ft-heavy-duty-lightweight-durable-zillagreen-hfzg5100yw-e-55-33-at-amazon

Though the link above takes you t amazon, you can buy the same hose from home Depot for the same price => https://www.homedepot.com/p/Flexzilla-5-8-in-x-100-ft-ZillaGreen-Garden-Hose-with-3-4-in-GHT-Fittings-HFZG5100YW-E/203549988

 

 

 

 

Details
Published: Tuesday, 23 March 2021 22:55
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PCI Bus:

PCI is a 2nd generation bus standard that was developed by Intel in 1990. By 1994, PCI became widely used in Pentium PCs. PCI-X which was an enhanced version of PCI was released with faster speeds. After PCI and PCI-X, came the enhanced PCI Express (or PCIE) which was the 3rd generation bus standard, with much faster speeds. This is what we have today in all modern devices. Original PCI and PCI-X are almost non existent.

There were multiple PCI standard as PCI 1.0 (5V signaling), PCI 2.0 (3.3V signaling, PCI-X) and PCI 3.0 (PCIE).The 2nd generation buses were PCI and enhanced version of PCI called PCI-X. The third generation of PCI is what we have today known as PCI Express (or PCIE). We'll look at 3 standards: PCI, PCI-X and PCI Express. like any other bus standard, PCI main objective is to transfer data between devices at highest rate possible.

Spec:

PCI 1.0: PCI bus originally had 33.33MHz clock with synchronous transfers. They had 32 bit wide bus, which gives it a peak transfer rate of 4byte*33.33=133MB/sec. It's 5V signalling, though 3.3V is also supported. It allowed multiple devices to share the same bus, which put a limit on the maximum frequency the bus can support. Clock speed of 33.33MHz (i.e time period=30ns) was only able to support 4-5 slots per bus, as beyond that load would be too high to meet timing. PCI later increased clock speed to 66MHz, which allowed only 1-2 slots per bus.

PCI 2.0: Later PCI-X came with 66MHz and 133MHz clock speeds, with more slots per bus.

PCI connector:

There are PCI connector cards which have contacts on each side of the connector. They have few notches to make sure that they fit only where they are compatible with the voltage supply (5V or 3.3V).

PCI bus transactions:

PCI bus traffic consists of a series of PCI bus transactions. Each transaction consists of an address phase followed by one or more data phases. The direction of the data phases may be from initiator to target (write transaction) or vice versa (read transaction), but all of the data phases must be in the same direction. Either party may pause or halt the data phases at any point.

Each PCI bus transaction

 

a local computer bus that attaches hardware devices in a

PCI Express:

Documents:

This by mindshare is a good one:

https://www.mindshare.com/files/resources/MindShare_Intro_to_PIPE_spec.pdf

 

Details
Published: Wednesday, 17 February 2021 21:04
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Genus:

Genus is the latest Synthesis tool from Cadence released somewhere around 2015. Before that RC (RTL Compiler) was the Synthesis tool from Cadence. Genus supposedly has better correlation with PnR and Timing tools from Cadence, as some of the engines that are used in those tools are used over here in Genus.

Legacy Vs CUI mode:

Genus uses CUI mode by default. Below are some diff b/w DC and Genus cmds:

DC Command
Genus Command
Notes
get_attribute get_property Most of DC "attribute" cmds have corresponding "property" cmds in Genus.
define_user_attribute define_attribute Other Cadence tools (Innovus/Tempus) use define_property (as expected), but surprisingly Genus doesn't support this, it has its own different define_attribute instead.
list_attributes list_property Genus. Tempus and Innovus all use list_property
set_user_attribute set_attribute Again, Genus uses "attribute" instead of "property". Here the argument order is different than in DC, objects need to come last in Genus
alias alias alias A B C works for DC but should be alias A "B C" for Genus. only double quote. Single quote doesn't work
report_path_group report_timing -cost_group * path group doesn't have a separate cmd in Genus
set_path_margin set_path_adjust  
get_cells, get_net, get_pins, get_lib_cells get_cells, get_net, get_pins, get_lib_cells same as DC (these are SDC cmds)
remove_designs * delete_obj /designs/* Genus has virtual linux style dir structure
read_verilog read_netlist same as DC
current_design Itop current_Design Itop same as DC
report_timing report_timing same as DC (these are SDC cmds)
set_false_path, set_multicycle_path, set_case_analysis, .. set_false_path, set_multicycle_path, set_case_analysis, .. same as DC (these are SDC cmds)
     
 SDC cmds are partially supported in genus.
Genus help:
On genus shell, type "help cmd_name" or "man cmd_name" and it will show the details of the cmd. Also, partial cmd name as "help *lib*" will show all cmds with lib in the name. Typing first few letters of cmd followed by a tab shows all possible cmds starting with those letters.
-------

Genus flow:

It's same flow as RC.

run Genus: script run.tcl

LEGACY MODE: genus -legacy_ui -f tcl/run.tcl -log /logs/top.log => prompt shows as genus@root:>

CUI MODE: genus -f tcl/run.tcl -log /logs/top.log => prompt shows as legacy_genus :/>

NOTE: Now you can use genus cmds on prompt. To see gui, type gui_show. (See section on "Cadence cmds" for details on CUI vs Legacy).

 

 

Steps:

1. Read Tech libs:

The default search path for libraries, scripts, and HDL files is the directory in which Genus is invoked. To specify non default path for library, set following attributes:

set_db lib_search_path

 

2. Read RTL:

3. elaborate => converts HDL rep into a netlist and performs High Level Opt (HLO). HLO here include Mux optimizations and Spasreness and redundancy opt

4. Read UPF, Timing constraints, DEF => UPF needs to be read only if there are multiple power domains in the design.

5. syn_gen => synthesize to generic gates. Performs data path and other HLO. Also does Mux opt, bit level opt, generic placer and physical buffering

6. syn_map => maps generic gates to tech gates. Does datapath arch selection, DP opt, Bit level opt, tech mapping, multibit opt and Timing/area CRR

7. syn_opt => performs bit level opt for area and timing

8. scan

9. syn_opt / iSpatial / Congestion prediction =>

 

Flow:

Clock cmds:

  • report_clocks => SDC cmd, uniform syntax
  • report_clock_gating => Reports clock-gating (CG) information for the design, and is useful to see all the statistics on where clk gating is not effectively applied.
    • report_clock_gating > clk_gating.rpt => This shows summarized info for # of CG (Genus vs Non-Genus), # of flops (Genus vs NonGenus gated/ungated), MultiBit Flops, etc. It reports # of leaf CG instances, followed by the # of Multi Stage CG (MSCG) instances (i.e where CG are NOT leaf CG anymore). MSCG has 2 options to indicate where should it cout from => from the flop or from the root.
      • -multi_stage_count_from_flop => this option counts from leaf flop, in which case Level 0 is the CG driving the flop, Level 1 is one level higher and so on.
      • -multi_stage_count_from_root => this other option is for counting from the root clk pin, in which case Level 1 is the top level of CG, level 2 is next lower level, until we get to the flop. NOTE: Here levels start from Level 0, while when counting from flop, we started with Level 1.
  • report_clock _tree_structure -out_file clks.rpt => This reports the clk tree hierarchy, which is very useful to see the whole clk tree structure. It shows different LEVELS of clk tree as L1, L2, etc. Start of a new level is determined if there is a clk gater, RTL instantiated gate, etc in design (i.e anything other than buffer and inverter, unless it's RTL instantiated buf/inv). There are many options to fine tune this report.
    • report_clock_tree_structure -show_sinks -clock_trees {clk1 clk2} => By default cmd shows the clk tree for all clks until the sink. These options show clk tree only for specified clks, with sinks included. NOTE: the same flops may appear under multiple clks, since 1 flop may be driven by multiple clks (depending on clk sdc file)
  • report

 

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