cpf - common power format
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- Last Updated: Thursday, 04 February 2021 01:56
- Published: Thursday, 04 February 2021 01:41
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CPF Syntax:
CPF is very similar to UPF in syntax. Since it's not used widely anymore, I'm listing an example below which shows the basic syntax. You can omit this whole section on CPF.
CPF cmd file Example:
Below is an example CPF file. The top level file is called TOP.cpf.
TOP.cpf =>
set_cpf_version 1.1
set_hierarchy_separator "/"
set_design chip_tb/chip_top/u_dig_top_wrapper/u_dig_top
##create top level PD
create_power_domain -name PD_TOP \
-default => includes everything in PD_TOP that isn't included explicitly in other domains
##create PD for all domains
#for PDMCU ( pdmcu = u_imp in arm_core + others attached to mcu),
create_power_domain -name PD_MCU \
-base_domains { PD_TOP } \
-instances { \
u_dig_top_pdmcu/u_ahb_to_apb u_ahb_peripheral_system u_dft u_sync_2s \
u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp } \
-shutoff_condition {!u_pmu_top/dig0_pm_if_ps_on | !u_pmu_top/dig0_pm_if_ps_good} => Anytime these signals are 0, all o/p ports of above instances goto "x", when running RTL sims with this cpf file (power aware rtl sims).
#similarly for other PD (PD_HFADC)
create_power_domain -name PD_HFADC \
-base_domains { PD_TOP } \
-instances { u_apb_peripheral_system/u_dig_adc/x_adc_hf } \
-shutoff_condition {!u_pmu_top/dig1_pm_if.ps_on | !u_pmu_top/dig1_pm_if.ps_good}
#PD for RAM/ROM IP do not have inst name, since they are mapped later with their cpf file
create_power_domain -name VD_RAM_MTB \
-base_domains { PD_TOP } \
-shutoff_condition { !(u_dig_top_wrapper/u_ram/PON&u_dig_top_wrap/u_ram/PGOOD) }
#####################
##create power nets
#primary voltage
create_ground_nets -nets { VSS }
create_power_nets -nets { VDD } -voltage 1.08
#switched voltages
create_power_nets -nets { VDD_mcu } -voltage 1.08 -internal
create_power_nets -nets { VDD_hfadc } -voltage 1.08 -internal
update_power_domain -name PD_TOP \
-primary_power_net VDD \
-primary_ground_net VSS
update_power_domain -name PD_MCU \
-primary_power_net VDD_mcu \
-primary_ground_net VSS
update_power_domain -name PD_HFADC \
-primary_power_net VDD_hfadc \
-primary_ground_net VSS
#create connections
#create pins for PDTOP aand connect it appr
create_global_connection -net VDD -pins { VDDNW } -domain {PD_TOP}
create_global_connection -net VDD -pins { VDD } -domain {PD_TOP}
create_global_connection -net VDD -pins { VDDC } -domain {PD_TOP}
create_global_connection -net VDDAR -pins { VDDAR } -domain {PD_TOP}
create_global_connection -net VDD -pins { VDDPR } -domain {PD_TOP}
create_global_connection -net VNWA -pins { VNWA } -domain {PD_TOP}
create_global_connection -net VDDS -pins { VDDS } -domain {PD_TOP}
create_global_connection -net VPP -pins { VPP } -domain {PD_TOP}
#similarly do it for PD_MCU and PD_HFADC
create_global_connection -net VDD_mcu -pins { VDDNW } -domain {PD_MCU}
create_global_connection -net VDD_mcu -pins { VDD } -domain {PD_MCU}
create_global_connection -net VDD -pins { VDDC } -domain {PD_MCU}
create_global_connection -net VDDAR -pins { VDDAR } -domain {PD_MCU}
create_global_connection -net VDD_mcu -pins { VDDPR } -domain {PD_MCU}
create_global_connection -net VNWA -pins { VNWA } -domain {PD_MCU}
create_global_connection -net VDDS -pins { VDDS } -domain {PD_MCU}
#create_global_connection -net VPP -pins { VPP } -domain PD_MCU => for efuse, not needed
#connect switch instances for both MCU and HFADC. Note: RTL for these switches don't have power ports, so we create power pins using this and then connect to allow it to have power aware behaviour. Only Pon, Pgood i/p pins, and ack o/p pins are in RTL of switches.
create_global_connection -net VDD_mcu -pins { VDD } -instances { u_dig_top/u_sw200u_mcu }
create_global_connection -net VDD -pins { VDDC} -instances { u_dig_top/u_sw200u_mcu }
#connect RAM IP pins
create_global_connection -net VNWA -pins { VNWA } -instances {digtop/../u_RAM }
create_global_connection -net VPP -pins { VPP } -instances {digtop/../u_RAM } => and so on for all power pins
##############
#RAMS/ROMS which have inbuilt support for power switch/isolation. They have separate cpf file which specifies power domain, iso rules etc. See below for such an ex:
-----------------
MY_RAM.cpf
set_macro_model MY_RAM => macro model names as something
# create_nominal_condition -name ON -voltage 0.75 -ground_voltage 0
create_nominal_condition -name ON -voltage 1.08 -ground_voltage 0
create_nominal_condition -name OFF -voltage 0 -ground_voltage 0 -state off
# 3 separate power domains with ports on specified power domains
create_power_domain -name PD_VDDPR_VSS -boundary_ports { FDI FCLRZ PGOOD AON \
PON RETON SO1 SO0 FCLK OFFP AGOOD FDO RETGOOD Q[31:0] } -default => default, so everything within module is in this PD
create_power_domain -name PD_VDDP_VSS -boundary_ports { ATPGM EZ TM WZ DFT CLK \
TEZ WRENZ[31:0] } -shutoff_condition { !(PON&PGOOD) } -base_domains { PD_VDDPR_VSS } => This is swiched PD
create_power_domain -name PD_VDDAR_VSS
create_isolation_rule -name ISOLATION -isolation_output low \
-from PD_VDDP_VSS -secondary_domain PD_VDDPR_VSS \
-isolation_condition { !(PON&PGOOD) } \
-pins { SO1 SO0 Q[31:0] }
update_power_domain -name PD_VDDPR_VSS -primary_power_net VDDPR -primary_ground_net VSS
update_power_domain -name PD_VDDP_VSS -primary_power_net VDDP -primary_ground_net VSS
update_power_domain -name PD_VDDAR_VSS -primary_power_net VDDAR -primary_ground_net VSS
create_power_mode -name NORMAL -default -domain_conditions { PD_VDDPR_VSS@ON \
PD_VDDP_VSS@ON PD_VDDAR_VSS@ON}
create_power_mode -name RETENTION -domain_conditions { PD_VDDPR_VSS@ON \
PD_VDDP_VSS@OFF PD_VDDAR_VSS@ON}
create_power_mode -name POWER_DOWN -domain_conditions { PD_VDDPR_VSS@OFF \
PD_VDDP_VSS@OFF PD_VDDAR_VSS@OFF }
end_macro_model
------------------
#now we map above cpf file with IP inst below
set_instance u_dig_top_wrapper/u_dig_top/u_dig_top_pdmcu/u_mica_mtbram/u_ram \
-domain_mapping { {PD_VDDAR_VSS PD_VDDAR} {PD_VDDPR_VSS PD_TOP} {PD_VDDP_VSS VD_RAM_MTB} } \
-port_mapping { {PON u_dig_top_wrapper/u_dig_top/u_dig_top_pdmcu/u_mica_mtbram/u_ram/PON} {PGOOD u_dig_top_wrapper/u_dig_top/u_dig_top_pdmcu/u_mica_mtbram/u_ram/PGOOD} } \ => maps ports on IP to those in PD domain, needed only if port names differ
-model MY_RAM => name of model in above cpf file
###############
##power switch rules
#PD_MCU
create_power_switch_rule -name ps_rule_1 \
-domain PD_MCU \
-external_power_net VDD
update_power_switch_rule -name ps_rule_1 \
-prefix ps1_ \
-enable_condition_1 u_pmu_top/dig0_pm_if.ps_on \
-acknowledge_receiver_1 u_pmu_top/dig0_pm_if.ps_on_ack \ => these provide ack signals for PA RTL sims. Needed so that state m/c can move forward, if it's waiting for ack signal.
-enable_condition_2 u_pmu_top/dig0_pm_if.ps_good \
-acknowledge_receiver_2 u_pmu_top/dig0_pm_if.ps_good_ack
#PD_HFADC
create_power_switch_rule -name ps_rule_2 \
-domain PD_HFADC \
-external_power_net VDD
update_power_switch_rule -name ps_rule_2 \
-prefix ps2_ \
-enable_condition_1 u_pmu_top/dig1_pm_if.ps_on \
-acknowledge_receiver_1 u_pmu_top/dig1_pm_if.ps_on_ack \
-enable_condition_2 u_pmu_top/dig1_pm_if.ps_good \
-acknowledge_receiver_2 u_pmu_top/dig1_pm_if.ps_good_ack
## isolation rules
#PD_MCU for o/p=High
create_isolation_rule -name iso_rule_high_1 \
-from { PD_MCU } => apply iso high cells to only 2 pins below
-pins { u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp/SLEEPING \
u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp/SLEEPDEEP \
} \
-isolation_output high \
-isolation_condition u_pmu_top/dig0_pm_if.iso_enable \ => These iso rules needed for PA RTL sims, so that o/p ports get correct values, instead of "x". NOTE: internal signals of powered dwn blocks will still be x.
-isolation_target from \
-exclude {}
update_isolation_rules -names { iso_rule_high_1 } \
-location from \
-within_hierarchy u_dig_top_pdmcu \
-prefix ISO1_HIGH_
#PD_MCU for all remianing o/p=low
create_isolation_rule -name iso_rule_3 \
-from { PD_MCU } -to { PD_TOP PD_HFADC VD_RAM } \ => Only apply iso low cells to o/p signals going from PD_MCU to PD_TOP etc, except SLEEPING and SLEEPDEEP o/p signal. All other o/p signals are w/o iso cells.
-isolation_output low \
-isolation_condition u_pmu_top/dig0_pm_if.iso_enable \
-isolation_target from \
-exclude { u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp/SLEEPING \
u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp/SLEEPDEEP \
}
update_isolation_rules -names { iso_rule_3 } \
-location from \
-within_hierarchy u_dig_top_pdmcu \
-prefix ISO3_LOW_
#PD_HFADC
create_isolation_rule -name iso_rule_2 \
-from { PD_HFADC } \
-isolation_output low \
-isolation_condition u_pmu_top/dig1_pm_if.iso_enable \
-isolation_target from \
-exclude {}
update_isolation_rules -names { iso_rule_2 } \
-location from \
-within_hierarchy u_apb_peripheral_system/u_dig_adc/x_adc_hf \
-prefix ISO2_
###########
## state retention rules
create_state_retention_rule -name ret_rule_1 \
-domain PD_MCU \ => all flops in this domain are treated as retention flops except for flops in "exclude" modules below
-restore_edge !u_pmu_top/dig0_pm_if.ret_enable \ => only 1 of save/restore needed
-save_edge u_pmu_top/dig0_pm_if.ret_enable \ => NOTE: save is opposite polarity of restore
-exclude u_dig_top_pdmcu/u_ahb_peripheral_system/u_flash_top/u_hardip ... \ => flops in these are excluded as retention
-target_type flop
###########
##nominal condition
create_nominal_condition -name on \
-voltage { 1.08 } \
-ground_voltage { 0 }
create_nominal_condition -name off \
-voltage { 0 } \
-ground_voltage { 0 }
update_nominal_condition -name on -library_set QC_MAX_1.2V_INDUSTRIAL_PD_TOP_timing => This lib set defined above comprising of .lib for all cells
update_nominal_condition -name off -library_set QC_MAX_1.2V_INDUSTRIAL_PD_TOP_timing
##power modes
create_power_mode -name run \
-default \
-domain_conditions { PD_TOP@on PD_MCU@on PD_HFADC@on }
create_power_mode -name sleep_hfadc_on \
-domain_conditions { PD_TOP@on PD_MCU@off PD_HFADC@on }
create_power_mode -name sleep_hfadc_off \
-domain_conditions { PD_TOP@on PD_MCU@off PD_HFADC@off }
## assertion controls
create_assertion_control -name ac1 -domains {PD_MCU} -type suspend
## This gets the cell to rerun "initial" block, when it powers up. This allows us to get init values of mem again.
set_sim_control -action power_up_replay \
-targets { * } \
-instances { \
u_dig_top_wrapper/u_dig_top/u_efuse_wrap \
} \
-modules {
ROM_INST \
}
###############
##define lib sets
define_library_set -name QC_MAX_1.2V -lib {a_W_150.lib ... c.lib}
define_library_set -name QC_MIN_1.2V -lib {a_S_-40.lib ... c.lib}
update_nominal_condition -name on \
-library_set QC_MAX_1.2V_INDUSTRIAL_timing
#include other tech cpf files
include "/db/.../CORE_RET.cpf" => CORE_RET.cpf has defines for state retention flops
i.e: (similarly for all other retention flops)
define_state_retention_cell -cells { RET_CELL_X1 } -cell_type \
CLK_HIGH -clock_pin CLK -save_function ~RETZ -power_switchable VDD -power \
VDDC -ground VSS
include "./CPF/MY_RAM.cpf" => CPF files for RAM/ROM etc
end_design
Running Power Aware Sims in RTL:
To run power aware sims in irun, add these extra args:
irun ....
-lps_cpf /db/dig_top_rtl_pasim.cpf \ => cpf file
-lps_pmode \
-lps_isoruleopt_warn \
-lps_isofilter_verbose \
-lps_logfile lps.log \
-lps_pa_model_on \
-lps_stime 1us \
-lps_verbose 3 \
-lps_iso_verbose \
-lps_verify \ => to turn on asserts in low power mode