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Published: Thursday, 04 February 2021 01:29

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Power Intent:

If you recall RTL coding in any HDL language, there is no way to model power connections in RTL. HDL langauges never had power definitions in them. Earlier in 1980's when HDL were being developed, all chips had single power, so there was no need to specify power connections at RTL level. These power connections to std cells were done in physical implementation phase, by the tools. It was very easy to do these, as power lines, VDD and VSS would just connect to power ports of std cells. The power grid for VDD, VSS would finally come to the pads of chip as ppower pins.

Earlier, power was not a concern, so power specific cmds in HDL were never considered. However, now power is a big concern, and a lot of effort goes into reducing power. This involves reducing lkg power of chip, by turning off portions of chip when not in use. Also, multiple voltage supply rails are being used, whose voltage range is dynamic. This asks for putting power definition in RTL to specify what logic is connected to what power supply. However, putting power connections in RTL reduces flexibility of RTL modeling, as it's supposed to focus more on functional aspect. So, standards were developed, which is a separate file with power intent of RTL coded in it, in a syntax called as power formats (PF). This PF file doesn't modify the RTL, but instead adds an abtract layer that defines how various code in RTL are connected to power supply. Simulation tools understand these PF, and simuate design with both RTL and PF in tandem. This is known as "power aware RTL sim" (PARTL Sim). These tools will thrown out an "x" from RTL code, when power supply to that piece of RTL code is OFF.  Thus it allows us to verify our design much before it goes thru physical implememtation. Also, Synthesis/Layout tools can also read this PF file and can know what piece of logic connects to what power supply. That keeps power supply connections easy and automated.

The netlist generated by synthesis/pnr tools can be non PG netlist (netlist which has no power ports for stdcells and modules), or PG netlist (one which has power ports VDD/VSS for stdcells and modules). We can specify what kind of netlist we want generated using options when writing netlist. When we had single power designs, PG netlists were not important as they all connected to single power supply, and didn't provide any extra info. However, now with advent of PF, we more commonly generate PG netlist, which shows power connections to each and every stdcell/macro. This allows us to run power aware simulations on gate level netlist (PAGLS sims). This extra sim allows us to find out if all power connections speciifed in PF file, were indeed done as intended. This sim doesn't need PF file, as all power connections are there in gate level netlist. 

Power Standards:

There are 2 PF standards in use today:

1. UPF (Unified Power format): The IEEE 1801 Unified Power Format (UPF) Standard establishes a set of commands used to specify the low-power design intent for electronic systems.

UPF manual can be downloaded from IEEE website. Std started developing in 2009. Current one is IEEE Std 1801-2017

See Design Compiler guide (Page 154) section 6-18 (specifying power intent) for details.

2. CPF: (Common Power format): This Format was introduced by Cadence, but shortly thereafter, UPF was proposed. Since UPF hasd backing of lot more companies, it was chosen as IEEE std, and CPF became less popular. The technical differences between the two formats are relatively minor. CPF is not really needed anymore as all tools support UPF now. I've a section on CPF, but it's for my reference only. You can omit it completely.

Terminology used in UPF/CPF:

Using UPF/CPF commands, you can specify the supply network, switches, isolation, retention, and other aspects relevant to power management of a chip design.

Power management (PM):  Power management enables a system to operate correctly in a given functional mode with the minimum power consumption. Implementation of pwr mgmt strategies require PM cells as level shifter, isolation, retention reg and repeaters to ensure that the design works correctly in the presence of diff pwr domains. PM cells may have single set of supply (i.e iso cell in destination PD), dual set of supply (i.e iso cell in source PD, level shifter, retention flops, pwr switch) or even more. Objects supplying pwr can be in various supply states, while objects consuming pwr can be in various power states. Supply state of supply port, supply net or supply set function is a combo of 2 values: state value (which may be OFF, UNDETERMINED, PARTIAL_ON and FULL_ON), and a voltage value (value in uV). Powr states are various legal states that objects can be in. These objects may be supply nets/ports/sets, PD, etc.

Below we briefly define various terms used in PM. We'll cover in more detail in UPF section. The terminology I've below is written for UPF, but applies to CPF as well.

1. Power domain:  It's defined group of elements in the logic hierarchy that share a common set of power supply needs. By default, all logic elements in a power domain use the same primary supply and primary ground, and may share other auxillary supplies such as isolation and retention supplies (explained later). A power domain may be single instance or collection of instances, powered by same supply. We define power domains in UPF to identify separate power regions in RTL. power domain identifies the uppermost inst of the domain. Every instance in design should be part of some power domain.

2. scope and extent: Each power domain has a scope and an extent. The scope is the level of logic hierarchy where the power domain exists. Scope in HDL refers to "region of HDL text where names may be defined".  Usually scope is module, submodule or blocks of statement, which can all be nested. Scope in UPF means the same. The extent is the set of logic elements that belong to the power domain and share the same power supply needs. In other words, the scope is the hierarchical level (instance of a module) where the power domain exists, whereas the extent is what all logic is contained within the power domain. So, with "set_scope" cmd, we specify which module of RTL the UPF file applies to. The scope in UPF is set to top module of RTL. If we want UPF file to be applied to some submodule in RTL, we have to set scope accordingly. Extent allows us to omit/include things within that scope that are prsent or absent in that power domain (i.e may be a set of logic within a submodule is supposed to be connected to some other power supply, in this case extent allows us to omit this from this power domain). Otherwise by default, power domain connects everything that is contained in that design hier to that supply to which that power domain is connected to.

Other way to define scope/extent is this: The instance in the logic hierarchy in which a power domain is defined is called the scope of the power domain. The set of instances that belong to a power domain are said to be the extent of that power domain. This distinction is important: while a given instance can be the scope of multiple power domains (i.e 1 power domain may be nested inside other power domain), it can be in the extent of one and only one power domain (since cell power suplly can only be connected to unique pwr supply, i.e VDD pin of cell can't be connected to 2 pwr supply pins). As a consequence of these definitions, all instances within the extent of a domain are necessarily within the scope of the domain or its descendants

3. nets and ports: Each scope or hierarchical level in the design has supply nets and supply ports. A supply net is a conductor that carries a supply voltage or ground throughout a given power domain. A supply port is a power supply connection point between two adjacent levels of the design hierarchy, between parent and child blocks of the hierarchy. We define supply nets and ports in UPF for power signals, even though these power signal nets/ports are absent in RTL. That is how UPF is able to define power intent of design. For macros or power management cells, these power ports may be specified in liberty or thru 'create_supply_port" upf cmds.

Supply net originates at a root supply driver, which can be an on-chip voltage regulator, an embedded power switch, a bias generator, or an off-chip supply source. One or more of these supply nets connect to a power switch, which has single output supply port. Supply network objects are created independent of power-domain definitions. This allows sharing of common components of the supply distribution network across multiple power domains.

4. Supply set: Related supply nets can be grouped into a supply set, with each supply net in the group providing one or more functions of the supply set. In other words, a supply set represents a collection of supply nets that provide a complete power source for one or more instances. Each supply set defines six standard functions: power, ground, pwell, nwell, deeppwell, and deepnwell. Each function represents a potential supply net connection to a corresponding portion of a transistor. Each function of a given supply set can be associated with a particular supply net that implements the function.

Mostly, power and ground are the only 2 supply nets that are needed (as pwell and nwell connections are tied internally to power/ground). Supply functions of a supply set, and the supply nets they represent, can be connected to instances in one of the following ways: explicitly, automatically, or implicitly. Connections are made downward, from ports or nets in the current scope to ports of descendant instances that are in the extent of the domain.

Supply sets may be primary, retention, isolation or level shifter supply sets, depending on what kind of cell they are meant for.

Supply Set Connections: Supply functions of a supply set, and the supply nets they represent, can be connected to instances in one of the following ways: explicitly, automatically, or implicitly. Connections are made downward, from ports or nets in the current scope to ports of descendant instances that are in the extent of the domain.

1. explicit connection:
2. automatic connection: In liberty file, each port has a pg_type as primary power, primary_ground, pwell, nwell, deeppwell, deepnwell. These are connected with matching function names in supply set
3. Implicit connection: An implicit connection connects the required functions of a supply set to cell instances that do not have explicit supply ports.

5. Supply variation: Supply ports, supply nets, and supply set functions take on values that consist of a state and a voltage. Named port states (see 6.4) and named power states (see 6.5) can be defined to represent the nominal voltages that a supply object may carry. These nominal voltage values are used also for determining whether level-shifting is required (see 6.45). In an implementation, the actual voltage of an object may vary around the nominal values. There are several sources of such variation. One source of variation is the accuracy of the supply. Supply variation can be modeled in UPF using the set_variation command (see 6.53). Supply variation is applied to nominal voltages to derive variation ranges for those voltages. Supply variation ranges (see 4.5.7) are used when determining whether level-shifting is needed.

6. Power states: As explained above, power states represent various operational modes of the domain's supply set. As an ex, a power domain may have 3 states: RUNNING, SLEEP and SHUTDOWN. In RUNNING, all supply sets may be at optimal voltage, while in SLEEPING, they might be at reduced voltages. In SHUTDOWN, primary supply may be OFF, while retention and isolation supplies may be ON). A value of 0 or L in HDL is considered ON or FULL_ON, while a value of 1 or H in HDL is considered OFF. X or Z may be considered UNDETERMINED or PARTIAL_ON depending on settings.

7. power switch: A power switch (or simply switch) is a device that turns on and turns off power for a supply net. A switch has an input supply net, an output supply net that can be switched on or off, and at least one input signal to control switching.

Supply network objects (supply ports, supply nets, and switches) are created within the logic hierarchy to provide connection points for a root supply and to propagate the value of a root supply throughout a portion of the design.

8. level shifter: Where a logic signal leaves one power domain and enters another at a substantially different supply voltage, a level-shifter cell must be present to convert the signal from the voltage swing of the first domain to that of the second domain.

9. isolation cell (aka clamp cell): Where a logic signal leaves a power domain and enters a different power domain, an isolation cell must be present to generate a known logic value during shutdown. If the voltage levels of the two domains are substantially different, the interface cell must perform both level shifting when the domain is powered up and isolation when the domain is powered down. A cell that can perform both functions is called an enable level shifter. Tools can optimize away redundant insertion of iso cells (i.e when nets are tied to constant logic, etc)

Isolation may be inserted for an input or for an output of the power domain. It's placed at i/p so that values coming into the power domain are deterministic even when the driver is powered down. They are needed at o/p so that values coming out of this power domain and going into other domain are deterministic even when driver is powered down. If we think about it, we may infer that isolation cells may need to be provided at i/p ports only, since o/p of a port may fan out to different with different clamp value requirements, so providing iso cells at all i/p ports only may work out. However, if we don't provide iso cells at o/p, then the "unknown" values will be going thru nets to all other blocks. These nets will need repeaters to carry the signal, and unknown inputs may cause short circuit current thru repeaters. So, we provide iso cells at both i/p and o/p of all blocks. Isolation cell's power supply for i/p ports is from same PD supply which is consuming it (as isolation is relevant only when the supply for that PD is on). However, this may be an issue for o/p ports, as they will become floating if driven by same power supply. So, we prefer to drive o/p ports with always on power supply, so that we are guaranteed valid iso values all the time??

An isolation cell operates in two modes: normal mode, in which it acts like a buffer, and isolation mode, in which it clamps its output to a defined value. An isolation enable signal determines the operational mode of an isolation cell at any given time.

9. retention reg/flops and memories: In a power domain that has power switching, any registers that are to retain data during shutdown must be implemented as retention registers. A retention register has a separate, always-on supply net, sometimes called the backup supply, which keeps the data stable in while the primary supply of the domain is shut down. Retention capability can be implemented for both registers and memories.

There are 2 flavors of retention reg:

1. Balloon-style retention: In a balloon-style retention register, the retained value is held in an additional latch, often called the balloon latch. In this case, the balloon element is not in the functional data-path of the register.Extra save/restore ports are needed to save or restore the values.
2. Master/slave-alive retention: In a master/slave-alive retention register, the retained value is held in the master or slave latch. In this case, the retention element is in the functional data-path of the register. This style of registers does not have save/restore ports, but may specify a retention condition that could take the register in and out of retention (i.e when power supply turned on/off).

10. Repeaters: Required when distance b/w driver and receiver is large. These repeaters should be on appr power domain.

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Published: Wednesday, 27 January 2021 07:47

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Investing in Stocks

As I've indicated in other sections, stocks are the only game in town. Even though Stocks are a ponzi scheme, as we can see based on returns they provide over a 30 year period, they are supported by the full backing and faith of the FED, which is a branch of the government. This branch of government can print infinite money to support the stock market, so stock market will be the winner of all the assets out there.

Should you invest in individual stocks?

There are several reasons why investing in individual stocks should be avoided at all costs. It's a scheme that's followed by a lot of people all over the world, who claim to have made big money, but it's mathematically very very low probabaility event. Of course some people like Warren Buffet have become super rich by investing in individual stocks. We'll discuss that later.

Below are some the reasons for not investing in individual stocks:

1. Predicting future of a company: No one can predict the future of a company, not even the founder of a company. As an example, check Steve Jobs. After introducing ipods in 2003, he kept on exchanging his higher priced stock options for a lower price, and accepting lower number of stock options in the process. He probably believed that his higher priced stock options would be worthless (as the stock may never get to that price). If he knew that his product and the company are going to be successful, he would have probably kept these higher priced stock options, and gotten way more richer. The stocks have gone up by 1000X from his exercise price in 2003. When the founder of the company who has all the insights, doesn't know the future of the company, who are we to predict the success of the company?

Here's another article about Tesla Founder Elon Musk, who on May 1, 2020 claimed that Tesla stock was over valued (even though he was the CEO at that time). If you were smart, you would have sold your Tesla stock, since there's no one who knows Tesla better than Elon Musk. Guess what? The stock went up 8 times from that price in less than 18 months.

https://www.msn.com/en-us/money/news/if-you-invested-1-000-when-elon-musk-said-the-price-of-tesla-shares-was-too-high-here-s-how-much-you-d-have-now/ar-AAWQACD

So this shows that all those stock pickers, wall street firms, etc predicting future of a company are just wasting everyone's time. Some of them will be right some of the time, just due to nature of probablity and statistics, but noone will be right all the time. God and only God knows the future !!

2. Life cycle of a company: There are more than 5K companies in US stock exchange. How do you figure which company you should invest in? Over long term, all companies either get bought out or go bankrupt. Starting from 1955, only 60 of the Fortune 500 companies remained in the list as of 2017. That means most companies got out of business, no matter how successful they were at a time. So, you not only have to invest in the right company, know the future of the company, but also time it so that you can exit at the top price for that company. That's impossible? If you could predict all these, you are already a GOD, and there's no need for money !!

3. Ponzi scheme: If you believe that Stock market is a ponzi scheme, then you should know that the market provides 10%-20% return with FED's support to this ponzi scheme. What FED guarantees is that it will take the market higher by a certain % every year. It doesn't guarantee any individual stock's return. You can think of it as FED saying that they will take the average price of all these stocks (that comprises the stock market) higher by 10% per year. Obviously since the mean is going up by 10%, some stocks will go up by >10%, while some stocks will go up by <10%. It's impossible to know which stocks will go up by more than 10% consistently. FED will save the market, but not any individual company (as it'll be seen as preferred treatment, and potentially illegal activity). Read the article on Fed's "stock market: Is it a Ponzi scheme" and "A dual class society". 

4. There's nothing called Value: You may think that value stocks will be the ones that will give you >10% (as Warren Buffet famously preaches). But these value stocks don't really have any value. Everything is way overpriced with respect to what any sane investor would pay for any of these businesses. The fact that they are trading on a stock exchange by it's very nature implies there is no value. They are all stocks with some random number written on them that determines their price. People start betting on both sides of that number, some betting that the number will go up, while some betting that the number will go down. That determines the daily price. It can keep trading like this till infinity, and the number has no meaning. The only thing that is guaranteed is that the average number of all the stocks will go up by 10% every year. The only real return that you get from any stock is the amount of money that it pays in dividend over your lifetime holding it.

5. No recovery from loss: Let's say you bought an individual stock that eventually went bankrupt or goes down by 90% or so. There is no way that you can recover this loss. Why? Because there's very little money left to invest in anything else. You will need a 900% gain to recover from a 90% loss. That kind of gains can't come in your entire lifetime with any sane investment. The money is almost all gone. No one can declare that a company will never ever go bankrupt. Warren Buffet keeps saying that he picks companies that are going to live for ever, and I've always scratched my head as to how can he guarantee that. To declare perpetual existence of a company, you have to know the future competition, future customers, future CEOs of that company, future shifts in taste of consumers, and a heck lot of future things both inside that company, as well as outside that company. If you can really predict all that, you are a GOD in human form and you don't need to be trading on stock market. You are way beyond that lowly humanly thing !!

Investing in Index Funds?

The only time when you lose money on a stock is when the company goes bankrupt. At that time, the number on that stock (i.e it's price) goes to 0 since it's not going to be traded anymore on the stock market. So, the price just disappears. Most of the companies eventually go bankrupt, so you have a high chance of losing all the money invested in that stock.

If you buy any large basket of stocks, you are piggybacking on the FED. You are basically saying that you will take the guaranteed return that FED is providing you with 0 risk. There's no science or IQ involved in choosing stocks. They are just random papers with some numbers written on them, that determine their price. The sum of all of these numbers is guaranteed by FED for a yearly +ve return, so stick to that.

This is how to think of the market return. Plot a graph, with Y axis being the % return per year and X axis being the year. FED puts a horizontal line with a Y=10%, implying stocks increase by 10% for each year. Now on any given day, there will be bunch of stocks with returns higher than 10%, and many with returns lower than 10%.

 FIXME: Put a graph ?

Stock trading in USA:

Once you have brokerage account opened (see details in brokerage section), you are ready to start trading. Before we get into details, let's see which are biggest holders of stocks. Ultimately it's we people who own most of the stocks in the world, but we usually buy it one of the 3 forms: as Mutual Fund (MF), ETF or individual stocks. Mutual Fund and ETF are explained below. These Mutual Fund and ETF are issued by some company and they are the ones who are listed as having owneership stake in these companies. These companies become the biggest owners of many of these public companies, and are listed as majority holders, even though in reality, their ETF/MF are ultimately owned by people.

The US stock market is $40T as of 2023. These are the 10 Companies with largest Assets under Management (AUM):

10 Largest Asset Management Companies in the World - Largest.org

Stocks to buy:

Well, as we learned in above section, there is no rationality in buying any individual stock. You should buy the whole market, or any index which represents a significant portion of the market. W500, SPY500, DJIA or anything like this will work. You can go for a limited index as index of 30 stocks, or an index that captures atleast 25% of the total market cap. So, top 10 stocks of the US market will also be fine as an index, if you want to do it on your own (i.e buy these top 10 stocks in proportion to their market cap, and adjust them every few days, but it's just lot of work). So, we'll buy ETF or mutual funds that charge a small fee, but allow us to trade a basket of stocks as 1 stock.

ETF vs Mutual Fund (MF):

A lot of money goes into buying stocks via mutual funds and ETF. As of 2020, total net assets of mutual funds registered in USA was $24T in 2020, compared to $5.5T in 1998. In contarst total net asset of ETF is $5.5T in 2020, compared to $0.1T in 2002. Of the total ETF market, 80% is equity ETF, 15% is Bond ETF, and remaining 5% is misc as commodities, convertibles, etc. Just in 2020 alone, $0.5T of money went in equity ETF, and as of Dec 2021, $0.8T of new money has already made it's way into equity ETF, which are both a record. So, you can see that ETF are growing in popularity much faster than mutual funds. A big reason for that is that ETFs can be traded anytime of day, which allows daytraders to get in and out with pretty low expenses.

ETF and Mutual Funds are not very different. They have a basket of stocks. They put this basket under a ticker symbol. You buy or sell this basket under the ticker symbol of that Fund. It's just like trading an individual stock. However, individual stocks don't charge you any annual fees. But these funds charge you an annual fee (known as expense ratio) which is a certain % of the fund amount. ETF charge you much lower fees (<0.1%) than Mutual Fund (usually 0.5%). Also, ETF can be bought or sold on the trade exchange anytime during the day, and their prices change continually. However, mutual funds only trade after market close at the set price. So, it's advantageous to buy ETF, as you can buy/sell at certain price.

Active Vs Passive:

Both ETF and MF can be actively managed by a group of professionals or be passively managed by a computer.

Actively managed ETFs and MF charge higher expense ratio as they need to pay a bunch of people managing ETF/MF. These people decide what all stocks to keep in the ETF/MF and keep on readjusting it.

Passively managed ETFs and MF charge lower expense ratio as they not managed actively by a person, but rather by a computer. They are also called index funds or index ETF as they track a particular index like S&P500, DOW30, or something like that. These ETFs and MF just mimmick those index, but have to pay some licensing fee to the company holding the rights to that index.

Most of the actively managed ETF and mutual funds are not able to beat an index fund, so no reason to pay a bunch of people managing ETF or mutual fund. They are wasting their time and your money.

Conclusion: Buy passively managed ETF and MF tracking a wide market index (i.e S&P500) as they have lower expense ratio. 90% of actively managed MF/ETF are not able to beat passive index funds. Among MF and ET, go for ETF as they not only charge lower fees, but also give you the control over buying/selling price.

There are thousands of ETF floated by various companies, mimicking various indices.These are the largest ETF companies, issuing a lot of ETF:

https://www.investopedia.com/articles/investing/080415/5-biggest-etf-companies.asp

• Blackrock (issuer of iShare ETF), Vanguard (largest ETF are VTI and VOO) and State Street (issuer of SPY ETF) are 3 biggest ETF issuers in US capturing 70% of US ETF market.
• Invesco (issuer of QQQ ETF) is at number 4. Charles Schwab comes at number 5, but is rapidly capturing market, with it's lowest "expense ratio" ETF. "SCHD" (US Dividend Equity ETF) is the largest ETF issued by Schwab.

Vanguard and Charles Schwab provide lowest cost ETF in general. When looking for any ETF, you will always find lowest fee ETF in that category to be from Vanguard or Schwab, so easy decision there. Vanguard has been known to be a leader in low cost ETF and MF, but schwab and others have been catching up lately.

This is the website with full details of all ETF: https://etfdb.com/etfs

This is a list of largest ETF: https://etfdb.com/compare/market-cap/

• Total ETF AUM globally was $10T as of May, 2023. These include all kinds of ETF as Equity, Bond, etc. In terms of asset class focus, equity ETFs currently compose 76% of the global ETF AUM, fixed income 21%, commodities ~3%, and currency and multi asset ETFs ~0.5%. Total Stock market cap is about $100T. So Stock ETFs have about 7% of the total equity market.
• US ETF AUM were $7T as of May, 2023 with ~3100 ETF listed on US exchanges. European market has $1.6T, while Asia region has $1.2T in ETF AUM. So, 70% of global ETF are actually US based.
• Top 3 ETF are all passive index tracking S&P500 => SPY, IVV and VOO totaling $1T in AUM. That speaks about the importance of S&P500 as an index compared to any other index of the world.
• Most traded ETF are TQQQ, SPY, QQQ with daily volume being > 10% of their ETF count.

These are terms to know when trading ETF:

• Expense ratio: Different ETF charge different expense ratio. Usually you should go with one with the lowest expense ratio. Expense ratio of most ETF is much lower those of equivalent MF. Some large Fidelity and Vanguard MF actually have expense ratio of 0.01%-0.02%, which is lower than equivalent ETF, so there are exceptions here and there. The only risk with "Expense ratio" is that it may change from time to time, so we are at the mercy of ETF issuers. Historically, Vanguard and Schwab have never raised their "Expense ratio" for their top ETF, so hopefully, we'll never have to liquidate those and move somewhere else.
• Spread: Other aspect of ETF is liquidity. If a ETF is highly traded, it's spread b/w buy and sell will be very small, so you don't lose much money when buying/selling these. However, if it's thinly traded (because not too many people have this), it may have a larger spread of say 10 cents/share or so. Let's say you buy a ETF at $500/share which has expense ratio of 0.1%. So, you pay a yearly fees of 50 cents/share. Now, if every time you buy or sell and you have a spread of 10 cents, your yearly cost is suddenly 70 cents/share (assuming you buy/sell once every year). This spread will eat into your profits.Also, a lower priced ETF will have larger spread as a percentage of ETF price than one with a higher price. So, it's advantageous to buy ETF with larger price. However, if you are a log term term buy and hold investor, then spreads don't matter as it's only 1 time expense. Expense ratio matter more, so you should go with low expense ratio ETF at cost of higher spread.
• Premium/discount: ETF have NAV value which is the value of all stocks in that ETF. Most of the times ETF will trade at exactly the same price as it's underlying stock holdings. But sometimes there is a small discrepancy. If the ETF trades for less than it's underlying NAV, it's said to be trading at a discount, while for the other way around, it's said to be trading at a premium. You should buy ETF on a down day, as you may get some discount. Here's more detail: https://www.fidelity.com/learning-center/investment-products/etf/premiums-discounts-etfs
• Dividend: The way ETF pay dividend is at the end of the quarter on a certain date. However, individual stocks underlying the ETF pay dividends thru out the quarter at different times. By not paying the dividend as soon it's avilable, we lose that opportunity to reinvest that dividend earlier. This dividend meanwhile sits in the ETF trust earning 0% interest. Dividend history of any ETF or stock can be found at: https://www.dividend.com

Best Equity Mutual Fund:

Even though I don't recommend Mutual funds in general, you will be surprised to know that there are a few "no expense" MF. There are also few MF whose expense ratio is actually lower than equivalent ETF, so it may be beneficial to own these MF over similar ETF. The only downside is that you can only buy it at closing price.

I've included few low cost MF below.

1. Fidelity "zero expense" Index funds:

In 2019, mutual fund giant Fidelity Investments shocked the market when it launched the first mutual funds with a zero expense ratio. Fideltiy introduced 4 "zero expense" index mutual funds.

• Fidelity ZERO Large Cap Index Fund (MUTF:FNILX) : FNILX “seeks to provide investment results that correspond to the total return of a broad range of large-capitalization U.S. companies" as per Fidelity. It has 506 stocks and looks similar to S&P500
  
• Fidelity ZERO Total Market Index Fund (MUTF:FZROX): FZROX "“seeks to provide investment results that correspond to the total return of a broad range of publicly traded companies in the US,” as per Fidelity. It has 2500 stocks and looks similar to Wilshire 5000.
  
• Fidelity ZERO International Index Fund (MUTF:FZILX: FZILX is an international counterpart of the domestic FNILX. It is a blend of developed and emerging markets with the latter representing over 20% of the fund’s weight. It has a 38% weight to Europe, while Japan and the U.K. combine for over 28%.
  
• Fidelity ZERO Extended Market Index Fund (MUTF:FZIPX): FZIPX focuses on mid- and small-cap stocks. It has 2000 stocks, and basically excludes the S&P 500 from its roster.
  

2. Fidelity 500 index fund (FXAIX):

This index fund tracks S&P500. Even though this is an index mutual fund, it's expense ratio is pretty small at 0.01%. It's even lower than the lowest cost ETF. It's provided by Fidelity.

3. Vanguard Institutional 500 Index Trust (VFFSX):

This is another mutual fund tracking S&P500 similar to Fidelity's FXAIX. It's expense ratio is also small at 0.01%.

4. Vanguard Total Stock Market Index Fund Institutional Plus Shares (VSMPX):

This is yet another MF tracking total stock market, whose expense ratio is small at 0.02%.

Best Equity ETF:

You should look to buy ETF with expense ratio < 0.1%. On $1M in stocks, 0.1% expense ratio would cost you about $1K/year, which is not great but still OK. There are few "zero cost" ETF too, though not that widespread.

"Zero" expense ETF:

This article tries to compare "zero expense" ETF with similar "low cost" ETF. Verdict is that the spread in these "zero expense" ETF more than eats up the "free part" and you end up paying more. Many of these 0% expense ratio funds are gimmick, since they raise the fees later. Or they are introductory, where they are "zero" for a while, but go to regular fees after some time.

https://etfmathguy.com/zero-and-negative-expense-ratio-etfs-have-arrived

As of Apr 2022, six ETFs charge no expense ratio, according to ETF Database. One of them is Bond ETF (BKLG), while 2 of them are Exchage Trade Notes (ETN) and NOT ETF. ETN don’t hold the securities in an index, but are unsecured debt securities that promise to pay the return of an underlying index minus the expense ratio. The Pacer iPath Gold ETN (GBUG), which seeks to track the return of the Barclays Gold 3-Month Index Total-Return; and the iPath Silver ETN (SBUG), which tracks the Barclays Silver 3 Month Index Total Return Index.If we leave these 3 aside, below are the 3equity ETF with "zero fees".

• BNY Mellon U.S. Large Cap Core Equity ETF (BKLC): This is the most widely avialable ETF with no expense ratio, i.e expense is 0%. However, the price of this ETF is about 1/6th the price of similar SPY ETF. This results in a larger spread. As an ex, consider SPY ETF at $500 and BKLC at $80. A spread of 5 cents in buy/sell bid results in 5X worse loss in BKLC. So, what you save in expense ratio, is lost in the spread when buying this. Also, the dividend in this is lower than the SPY ETF. So, I wouldn't recommend this ETF, even with it's 0% expense ratio. You need to get at least the same dividend as S&P 500, or else it's not worth the risk.

• Next are the 2 SoFi ETF. Both have temporarily waived fees until at least June 30, 2020. So, these are dubious, as they will raise fees, and we won't know by how much. So, best to avoid these too.
  
  • SoFi Select 500 ETF (SFY): Similar to the S&P 500 Growth Index in that it is composed of the 500 largest publicly traded U.S. companies. Similar to the iShares S&P 500 Growth ETF (IVW)
  • SoFi Next 500 ETF (SFYX): Composed of 500 mid-cap U.S. companies weighted on not just market capitalization but three growth signals. This is a similar fund to the SPDR S&P MIDCAP 400 ETF (MDY)

Below are best low cost equity ETF to buy (The lowest cost ETF are around 0.03%):

ETF mimicking S&P 500 index:

These mimick S&P 500 index. Their expense ratio can't go below 0.03% as this is the licensing fees ETF have to pay to S&P. Their yield is about 1.3% as of 2021.

1. SPDR S&P 500 index ETF (SPY):

This is the most popular ETF, but it has a higher expense ratio of 0.09%. You can can get same S&P500 ETF with less than half the fees, so don't buy this. In past there weren't any lower cost alternative, so this ETF thrived, but now you have cheaper options, with same return. However, it's stil the largest equity ETF as of 2021, because most people hear about this ETF only and don't know that alternatives exist.

2. ishares core S&P 500 ETF (IVV):

This is similar to SPY, but with a lower expense ratio of 0.03%. This is one of the lowest cost ETF mimicking S&P 500, so go with this, or with the next one.

3. Vanguard S&P 500 ETF (VOO):

This is similar to IVV, and it's expense ratio is also 0.03%. I assume IVV may be better, as the price of IVV is 10% higher than that of VOO, so you lose a little less in the spread. Personally, I've bought VOO, as the difference is probably negligible. Also, VOO is product of Vanguard, which is what I personally prefer.

ETF mimicking Nasdaq 100 index:

As we saw in our earlier section that Nasdaq has beaten S&P500 over all periods of > 10 years of holding, It lost to S&P 500 only when you bought at peak of stock market in 2000. So, if the stock market (i.e Wilshire 5000) is more than 10% down from it's peak, then it's time to start putting some money in Nasdaq ETF, as you are guaranteed higher returns than S&P500 (assuming FED will pumping money into this ponzi scheme). Nasdaq ETF in general have much higher expense ratio (I'm not sure why, since it's also passively managed). However dividend yield for this is only 0.5% as most stocks don't pay any dividend. Below are ETF mimicking nasdaq 100 (which is a subset of Nasdaq stock market).

1. Invesco QQQ Trust ETF (QQQ):

This is the most popular ETF for Nasdaq 100, but it has a higher expense ratio of 0.2%. It's structured as a trust fund. I don't know of any difference it makes for an investor. This is among the top 5 equity ETF. It has high liquidity. It's spread is small at 1 cent. It used to trade under symbol "QQQQ" but since has dropped 1 Q.

2. Invesco Nasdaq 100 ETF (QQQM):

This is issued by same company and is same as QQQ except that it's expense ratio is 0.15%, and it's an open ended ETF. It is called as "Triple Q Mini". It has a larger spread of 3 cents as it's thinly traded (it has < 1% of AUM than QQQ) . However, QQQM is preferred and there is no reason to hold QQQ in favor of QQQM. QQQM is ideal for long term investors, and gradually adding to this ETF at drops of 10% or more of the market (i.e 10% drop in S&P500) would serve well in stock market ponzi scheme.

ETF mimicking Total US Stock market index:

We may also look into US total equity market index mimicking Wilshire 5000.

1.Vanguard Total Stock Market ETF (VTI):

Expense ratio is 0.03%, and this is among the top 5 equity ETF (as of Jan, 2022, expense ratio shows as 0.02% on most websites, probably, because the index has gone up, while their annual costs might have remained the same). However, the yield here is 10% lower than S&P500, and the difference in return b/w this and S&P500 is small. So, better to stick with S&P500 over this. There is an excellent article comparing it to SPY:

https://seekingalpha.com/article/4438495-spy-vs-vti-etf-better-buy

2. Schwab US Broad Market ETF (SCHB):

Similar to VTI, but tracks only 1500 companies. Expense ratio is 0.03%, and it has Schwab's name behind it.

Other low cost or high return ETF:

1. Ark Innovation ETF (ARKK):

Ark Innovation has couple of ETF, but this is the one that is the most popular and hot ETF. It's expense ratio is high at 0.75%. It was incepted in 2014, and in last 8 years, it has given returns that blow even Warren Buffet's returns. It's rock star manager, Cathie Woods actively manages this ETF, and tries to find highly innovative and disruptive companies anywhere in the world that will yield insane returns. I'm not a fan of this ETF, as this ETF was formed during an equally insane bull market, so basket of risky junk stocks will almost always will give you better returns than sane ones. This ETF needs to go thru 30%-50% market correction in order to find out it's real returns.

UPDATE: As of Jan 2022, ARKK is already down 55%, while S&P is down only 5% from it's peak. That speaks to the insane returns that a bull market can provide to non-sense funds. If it wasn't for Tesla stock in it's holdings, ARKK would have given 8 year return less than that of S&P500. Most of these ETFs get lucky in 1 stock that gives them 100X or 1000X returns. In such cases, even if all the other stocks go bankrupt, the fund is still able to deliver a decent return, and their manager get a rock star status and a multi million dollar pay check.

2. RoundHill's Magnificent 7 ETF (MAGS):

This is the Mag 7 ETF (7 stocks being AAPL, MSFT, NVDA, TSLA, META, GOOG, AMZN). It provides equal weighting to all stocks (though tsla is at 10%, while others are at 15%). Launched in 2023, it's expense ratio is 0.29%. Not worth it, as it's not diversified enough. It came into existence when biggest US companies were giving the biggest gains in stock market. Over time, it will give almost same return as Nasdaq 100.

3. iShare Top 20 US Stock ETF (TOPT):

This is exactly what the name says => Top 20 US stocks by market cap. This was launched in Oct, 2024, on same lines as Mag7. However, this ETF is diversified enough as top 20 US companies make up ~ 50% of S&P500 market cap.  Expense ratio is 0.2%, so similar to QQQ, but not as diversified. Link => https://www.ishares.com/us/products/339779/ishares-top-20-u-s-stocks-etf

4. State Street S&P500 High Dividend ETF (SPYD):

This ETF, introduced in 2015, takes the 80 highest yielding Stocks in S&P500. The only difference compared to S&P500 is that it applies equal weighting to all 80 components, so all 80 stocks have weighing of 1%-1.5%. Expense ratio is low at 0.07%. Dividend is high at 4.5% as of 2025. This ETF has gone up by 50% in last 10 years, which looks pretty low, but once you add back reinvested dividends, the yield is ~10% from 2015-2025, which is still lower than SPY return of 12%. .However, it's much less volatile, due to it's high dividend. This ETF also has REITs in it, so it's price appreciation is very low. No added value in this ETF. Better dividend paying alternative is SCHD ETF below.

5. Schwab US Dividend ETF (SCHD):

This ETF, introduced in 2011, tracks Dow Jones US Dividend 100 index, which includes 100 U.S. stocks that exhibit consistent dividend payments. It's universe only includes firms with 10+ yrs of dividend history, along with strong fundamentals, low payout ratio, sustainable dividends, etc. Due to this approach, SCHD very easily beats SPYD. It's market cap weighted, and dividend yield is > 4% as of Apr, 2025. It's expense ratio is lower at 0.06%. If you are looking for dividends, this is the best dividend ETF to own, as dividends have increased by > 11%/yr. However SCHD has underperformed VOO over the last 10 years.

SCHD Vs VOO: https://portfolioslab.com/tools/stock-comparison/SCHD/VOO

Link on SCHD pros => https://seekingalpha.com/article/4773173-schd-buy-the-dip-and-call-it-a-day

6. Vanguard High Dividend Yield ETF (VYM):

This ETF introduced in 2006, tracks FTSE High Dividend Yield Index. It has > 500 stocks, so is more diversified, However, yield is considerably lower than SCHD, and total return has also been lower compared to SCHD. Expense is same as SCHD, so no reason to buy VYM over SCHD.

Leveraged ETF:

Leveraged ETF are latest rage (as in leve-rage), as they amplify your returns by a factor > 1. So, if you lose 10% in a day, a 3X levereged ETF will lose 30% for the day. Conversely if you gain 10% in a day, a 3X levereged ETF will gain 30% for the day. You have all kinds of leveraged ETF from 2X to 4X with all popular indices in both long and short direction. Last 10 years have seen a big bull market with no corrections, which have given compounded returns of >30% for these "long" ETF. These, as the name implies, are long ETF, i.e they go long on the stocks, meaning your returns are in same direction as the un leveraged ETF. There is also short ETF, which goes in opposite direction of the underlying non-leveraged ETF, i.e if the underlying ETF goes up, your leveraged goes down and vice versa. This is essentially like shorting the market, except that you are leveraging to amplify the return. Since there is no free lunch, and someone else is taking the risk to amplify your returns, these ETF charge you lot higher fees, usually at 1%.

The below article shows how much return an ETF named TQQQ which is a 3X leveraged version of QQQ ETF has given to it's holders.

https://www.optimizedportfolio.com/tqqq/

As can be seen it gave 50% annual return to it's holders. A $10K sum invested in TQQQ turned into $600K in 10 years.However if you had invested your money in the TQQQ ETF right before 2000 crash, you would not recover your money in your lifetime. However, as shown in link above, if you had hypothetically invested in TQQQ in 1980, you would have managed to get 4X the return of Nasdaq, even with all the ups and downs. So, why are leveraged ETF not considered long term investement?

Reason is that leveraged ETF will eventually go down down to 0, over long time horizon, so you are essentially guaranteed 100%. Why it happens, is loss due to ups and downs of market, and these ETF being adjusted on a daily basis. You can think of ups and downs as oscillations, which take energy out of these leveraged ETF. Market going up increases the energy in leveraged ETF, but these oscillations keep on sucking energy ot. Larger the oscillations, larger the energy sucked. Eventually, oscillation energy may overwhelm the energy due to markets moving higher. More the ups and downs, quicker will the leveraged ETF go down to 0.

Since 2009, rules of leveraging have changed. FED has now guaranteed that markets will only go higher, the oscillations will be small, and they will move quick to recover any losses happening in market. In fact, FED is encouraging leveraging by providing money at close to 0% interest. This means that leveraged ETF may keep on outperforming non leveraged ETF as long as the FED has the power to print money. However, if a sane government comes into rule, there may be no FED, nor any of their money printing press. So, we should be cautious with these extremely dangerous products. They have the risk to wipe you off completely if sanity ever returns.

This article discusses some more: https://seekingalpha.com/article/4378063-tqqq-is-high-risk-low-reward-investment

So, the lesson with leveraged ETF is to use them for only a very small portion of your portfolio, and that also after a 30% crash from the top.

These are few leveraged ETF: The link shows the top ones: https://etfdb.com/etfs/leveraged/equity/

ProShares Ultra are 2X leveraged, while ProShares UltraPro are 3X leveraged. If they don't have the word "short" in the name, then they are "long" ETF, while ones with word "short" are short ETF. So, in a bull market, short ETF suffer badly, while in a bear market, they give great return. Since we are investing in the stock market for ever, "short" ETF have no place in our portfolio (they will eventually go down to zero).

1. S&P 500: ProShares Ultra S&P500 (SSO) is 2X leveraged, while ProShares UltraPro S&P500 (UPRO) is 3X leveraged version of SPY. Their expense ratio is 0.93% for both, and dividend is close to 0.01%.

2. Nasdaq 100: ProShares Ultra QQQ (QLD) is 2X leveraged, while ProShares UltraPro QQQ (TQQQ) is 3X leveraged version of QQQ. Their expense ratio is 0.95% for both, and dividend is close to 0.01%.

If you really have to invest in leveraged ETF, TQQQ is the best option of all, as it's most highly traded leveraged ETF (with $18B in AUM), and allows you to maximize your return by going all in.

Which index funds to stick to?

So, now that we have looked at index ETF and MF, which index should we try to mimic? Let's see below.

SPY ETF:

Below is the dividend history of SPY ETF, which is longest one to track S&P500: https://www.dividend.com/etfs/spy-spdr-s-p-500-etf-trust/

In 1994, dividend for SPY was $1.17/unit, while in 2021, dividend was $5.65/unit. So, dividend went up almost 5X in 28 years, implying an average annual growth of 5%-6% in dividend. In 2000, dividend was $1.45/unit. while in 2010, dividend was $2.2/unit. So, dividend used to grow by 4% a year before 2010, but since 2010, it has really sped up, and increasing at a rate of 8% a year. This means, more and more companies are maxing out on their dividend, and room for further dividend growth is getting smaller. This is unsustainable dividend growth. Dividend can grow only by same rate as GDP, as revenues and profit increase by same rate as GDP, so it's logical that dividends would also go up by same rate. Also, other thing to note is that dividend used to yield 2.5%/unit (price=$45/unit in 1994) in 1990s, but now it yields 1.25%/unit (price=$450/unit as of 2021). This implies that not only have dividends been growing faster, but stock prices have been growing even faster (dividends went up 5X while stock prices went up 10X).

QQQ ETF:

Below is the dividend history of QQQ ETF, which is longest one to track Nasdaq100: https://www.dividend.com/etfs/qqq-invesco-qqq-trust/

Unfortunately it shows dividend data starting from 2008, even though this was launched in 1999. In 2008, dividend was $0.14/unit, while in 2021, dividend was $1.7/unit. So, it went 12X in 14 years, implying an average annual growth of 20% in dividend, which is insane. The dividend yield used to be paltry 0.3%/unit (price=$40/unit in 2008), but even today it yields a lowly 0.4%/unit (price=$400/unit in 2021). So, QQQ yield has gone up, in contrast to SPY yield which has gone down. Meanwhile, QQQ has also gone up 10X in last 15 years, while it took SPY 30 years to get to 10X. So, QQQ has been growing much faster than SPY, and yields between SPY and QQQ are narrowing at the same time.

Conclusion: So, it would make sense to invest into both S&P500 and Nasdaq100. The best way to start would be to mimic S&P500 index. Once S&P500 has crashed 20% from the peak, we should start reducing S&P500 index and start increasing Nasdaq100 index. At 40% crash of S&P500 index, we should be investing 100% into Nasdaq100 index. Between 20% to 40% crash of S&P500 index, we should linearly go from 100% to 0% for S&P500, and from 0% to 100% for Nasdaq100 index. This would give a good mix of dividend yield and stock price appreciation.

So, the 3 ETF to stick to are:

1. QQQM: High price appreciation, but low dividend of 0.5%. However, QQQM gave you the highest return over the last 30 years (1%/yr more return than VOO).
2. VOO: Tracks S&P500, with decent dividend of 1.5%. VOO has given decent return of 10% over the last 40 years.
3. SCHD: Low price appreciation, but high dividend of 4%. SCHD has given the least return over the last 15 years (1%/yr less return than VOO). SCHD is more for people nearing retirement, who are looking for a huge cash flow so that they don't have to sell any stocks. With $2.5M invested in SCHD in retirement, you can get $100K in dividends which might suffice for decent life. With QQQM and VOO portfolio, you'll need upwards of $10M to retire.

Individual stocks:

After a long rambling on why not to buy individual stock, there may still be the testosterone gushing in some of us that wants to try something manly. In that case, it's OK to invest < 10% of your total holdings in individual stocks. Also, never invest > 1% of your portfolio in a single stock, no matter how much of a slam dunk it appears. We are NOT warren buffet. Always assume that you may completely lose money on this 10%. But we'll make up for the loss by remaining invested in whole of the market in the remaining 90%, which will always overcome the 10% loss, and take us back to positive return.

I maintain a WatchList of stocks that look decent, strong companies with low chance of going bankrupt. Look under "WatchList" section.

Selected Stocks to buy: https://www.simplysafedividends.com/intelligent-income/posts/1-living-off-dividends-in-retirement

According to the Wall Street Journal, over the past 50 years the S&P 500’s dividends grew at an average 5.7% per year, outpacing the average 4.1% inflation rate.

https://www.simplysafedividends.com/intelligent-income/posts/6-dividend-aristocrats

53 companies listed here. Most of them have dividends > 2%.

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Wishing you a Happy participation in the biggest Govt run Ponzi scheme !!

Details

Published: Wednesday, 27 January 2021 06:15

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Delay thru the Transistor:

A very important metric in digital design is the delay thru any gate. This determines the speed of the chip, since less the delay thru a transistor, faster is the gate, and less is the time it takes for a signal to go from one flop to next flop, resulting in a chip that could run faster.

In previous section on "solid state devices", we saw the eqn for Transistor current. Since this current determines the delay thru a transistor, any change in of these parameters of the eqn could cause a change in current and hence a change in delay. These are the 3 input conditions that could affect transistor delay:

1. Process: Any change in process parameters µ, C_ox, W, L or V_TH could cause a change in delay thru transistor. These 5 process parameters vary depending on the fabrication process used. The first 4 process parameters affect delay thru transistor linearly, while Threshold voltage affects the delay as square and so has a more pronounced effect. A "fast" or "hot" process corner is one where these parameters change in a way, that makes the transistor run faster. Converse is true for a "slow" or "cold" process corner. Fabs can usually target their process to their customer's needs.
2. Voltage: Any change in the voltage applied to terminals of transistor could cause a change in delay. Here we show V_gs only, but V_ds could cause a change. Both of these voltage values are eventually dependent on supply Voltage (VDD), so the supply voltage at the transistor terminals could impact delay thru it. Highre the voltage, higher the transistor current and lower the delay.
3. Temperature: From above eqn, it's not apparent that Temperature could cause any change in current. But if we look carefully, we notice that some process parameters are actually dependent on Temperature. 2 of such params are Mobility (µ) and Threshold Voltage (V_TH).
   1. Mobility (µ): Mobility of electrons or holes is determined by how fast they are able to move thru any medium. As we saw in Resistance and Capacitance section, it's change in avg speed with change in Electric field. Recall that mobility of any charged particle is q*t/m, so as charge travels more before colliding with anything, it gets to a higher speed, and hence it's mobility is higher. In a lattice structure of a compound or element, how far these electrons or holes travel depends on the lattice structure and size of atoms around these moving electrons/holes. In general, as Temp increases, these electrons/holes get more energy and are more agitated. So, they travel with faster speed, but also hit the lattice structure more often. The final effect is that mobility decreases with higher Temperature. Current decreases with lower mobility. So, transistor gets slower with higher temperature.
   2. Threshold Voltage (V_TH): Threshold Voltage of a transistor was explained in "solid state device" section. It's basically the barrier that electrons/holes in conduction band have to clear. As temp increases, more of these electron/hole pairs get in conduction band, due to higher energy. This allows more electron/hole to cross the hump, resulting in higher current, or effectively lower Threshold Voltage. In general, as Temp increases, threshold voltage gets lower as  carrier concentration increases. Current increases with lower V_TH as current has square dependency on gate overdrive voltage. So, transistor gets faster with higher temperature.
   3. Net Effect: So, we see that these 2 effects have opposing effects with increase in Temp, where mobility causes transistors to slow down, while Threshold Voltage causes transistors to speed up. Net Effect is hard to gauge w/o knowing the exact relation of these 2 factors with Temp. In the past for designs 180nm and above, it used to be that increasing temperature used to make transistors slow, meaning mobility won over Threshold Voltage. We can see from transistor Current eqn, that if VDD is lot more than V_TH , then even with square dependence, the effect of  V_TH change will be muted. As an ex, consider case where  V_TH is 10% of VDD. Now as Temp goes up, Vth will come down. A 20% reduction in  V_TH will cause change of ( (VDD-0.1VDD)/(VDD-0.12VDD))^2 = (0.9/0.88)^2 = 1.04 or 4% increase in Drive current. This is assuming V_TH is going down linearly with inc in Temp. However, a 20% reduction in µ will cause a 20% decrease in drive current (assuming µ is going down linearly with inc in Temp) over same Temp increase. So, net effect will be that transistor will get slower by 15% as Temp increases in that range. This was always the expected behaviour.
      
      • Temperature Inversion: We saw above that Inc in Temp resulted in slowdown of transistor for 180nm and above. However, with sub 180nm design, the trend started inverting, and transistors started running faster at higher temperatures, especially at lower voltages. This was due to the fact that VDD came down significantly with scaling of transistors, but V_TH came down only a little. So, now Vth was about 50% of VDD. With increasing Temp, a 20% reduction in  V_TH will cause change of ( (VDD-0.5VDD)/(VDD-0.6VDD))^2 = (0.5/0.4)^2 = 1.56 or 56% increase in Drive current. This is assuming V_TH is going down linearly with inc in Temp. However, a 20% reduction in µ will still cause the same 20% decrease in drive current (assuming µ is going down linearly with inc in Temp) over same Temp increase. So, net effect will be that transistor will get faster by 30% as Temp increases in that range.  This phenomenon of transistors getting faster at higher temp was an anamoly and came to be known as temperature inversion. 

Delay thru R and C:

Above 3 conditions not only affect the delay thru a transistor, but also affects the delay thru wires which have resistance and capacitance in them. Thus we have to consider the effect of PVT on Resistance (R) and Capacitance (C) too. When process is making a transistor weaker, there's no rule that says that R, C will get slower too (i.e more resistance and higher capacitance). We'll have to look at equations for R, C to see their dependency on process, Voltage and Temperature.

1. Process: Process impacts R, C both ways, however it's precise correlation with transistor is hard to gauge. We usually get a range of R, C and use those limits to bound the box for R, C. Note that R and C usually move in opposite direction. For ex, a process that increases R because it's making the wires thinner will decrease C as wires will have more distance between them. So, the product R, C may not change much across process variations.
   1. With lower nm tech, variations in metals/vias R,C are significant. There are also a lot more R,C process corners than just Rmin,Cmin and Rmax,Cmax. With 2 or more masks on same metal layer (in FinFets <16nm), the variations are even more pronounced as the 2 masks may shift on the same metal layer, causing more variations. Most of the times, it's not possible to run timing tools for all R,C corners. So, we just pick few R,C corners and then apply a BEOL margin to account for other corners which we may not have run, but may show worse performance. This margin is only applied for hold timing, as hold is more critical (failing to meet hold timing will result in chip not working).
2. Voltage: Voltage has negligible impact on R, C to first order. Need to have an equation FIXME ?
3. Temperature: Resistance increases with Temperature. However, capacitance doesn't have a clear relation with Temperature and will go up or down depending on dielectrics involved. Need to find more about C Vs T ? FIXME ?

Final Delay through a path involving Transistors and Wires:

Final delay thru a path depends on P, V, T. For "weak" P, transistors get weak, as well as R,C get weak too. We don't mention R,C separately, as it's assumed that N (normal) process means typical transistor, typical R, and typical C. However, in reality we may want to consider variants, where for a Strong process, transistor may be strong, but R, C may not be as strong.

PVT ranges:

The 3 PVT inputs that affect delay of circuits are very important in determining proper functioning of circuits. In digital circuits, they are used to check if all the paths in digital circuits meet timing. We run timing tools on our design to make sure our design meets timing. We check timing at various PVT corners. More details are in STA section.

We run timing at extreme PVT corners that our design can possibly be exposed to. We also have typical corner that the design is supposed to be exposed when being in a typical environment, but usually we don't run STA on this typical corner. Let's see the range of these PVT corners:

Process: For process we define a fast process corner and a slow process corner. fast process corner is where all transistors are supposed to be running faster, while slow corner is one where all transistors are supposed to be running slower. However how fast is fast corner really? For that we use a metric called 3 sigma variation. We draw a plot of all transistors across various dies, with current on X axis and number of transistors on Y axis. This gives us a gaussian plot. From this plot, we take 3 sigma variation from mean. The -3 sigma point gives us slow corner, while +3 sigma point gives us fast corner. 99.7% of the transistors lie within -3 sigma to +3 sigma range. So, we are willing to sacrifice the remaining o.3% of the chips if they don't work in real silicon. Since we have both PMOS and NMOS, we define fast and slow for PMOS and NMOS separately. So, we have 4 combinations:

1. fast fast (FF): This is the corner where both NMOS and PMOS are fast
2. slow slow (SS): This is the corner where both NMOS and PMOS are slow
3. fast slow (FS): This is the corner where NMOS is fast but PMOS is slow. This doesn't really happen in real silicon by itself, though it's sometimes done on purpose.
4. slow fast (SF): This is the corner where NMOS is slow but PMOS is fast. This doesn't really happen in real silicon by itself, though it's sometimes done on purpose.

Voltage: When we run STA at a certain voltage, we always mean the voltage at the transistor pins. It's not the voltage at chip pins. For smaller chips or ones which don't draw a whole lot of current for digital block, the difference is voltage b/w chip pins and tarnsistor pins is not much and can be ignored. However for digital SOC which have billions of transistors and run at 1V or below, the voltage difference can be substantial. We usually run some sims to figure out voltage at transistor pins. Once we know the voltage at transistor pins, we apply a some margin for PMU voltage overshoot and undershoot. Chip pins are usually driven by a PMU, whose all job is to keep the voltage fixed at specified level. Even then we account for some voltage overshoot/undershoot. As a rule of thumb, we apply +/-10% voltage overshoot and undershoot for chips that have a small digital core having less than a million transistors, and running at > 1V. This +/-10% also accounts for the IR drop that may occur on chip. This 10% rule of thumb is true only for small digital cores. For large digital SOCs, we run more detailed simulations.

Temperature: For temperature, we usually consider a range of -40C to +150C depending on what kind of temperature extremes we think the chip may be exposed to. The ambient temperature (temperature of environment) may not go to such extremes but the temperature of the transistor itself may go to large extremes. -40C to +150C provides us enough buffer for such temperature extremes. -25C to +85C is other temperature range that's seen in smaller chips, which aren't consuming too much power (i.e embedded chips), so a smaller range suffices for those. Lower temperatures are limited to ambient temp, as temp of chip can't go below ambient Temp (as chips will usually generate heat). But for higher temperatures, we go much higher than ambient Temps. That guarantees that nothing will break on the chip at higher Temps. . Of course, for people living in very cold climates, there's no guarantee that the chip will work :(

PVT Corners: We define 3 PVT corners.

1. typ: This is the TYP corner, where PVT is at it's typical value. So, Process = TT which means NMOS and PMOS are at their typical process value (i.e typical speed), Voltage = Typical voltage that the design is supposed to run at and Temperature = typical room temperature which is taken as 27C. Here we take R, C at their typical values, even though we know that if NMOS/PMOS are at their typ values, R,C may not be necessarily at their typ values.

2. min: This is the MIN delay corner where transistors are supposed to be at their minimum delay (i.e fastest). So, Process = FF which means NMOS and PMOS are at their fast process value (i.e fast speed), Voltage = Maximum voltage that the design is supposed to be exposed to (maximum PMU voltage overshoot) and Temperature = lowest temperature which is taken as -40C. However for lower nm nodes (<180nm) operating at very low voltages (< 1V), Temperature inversion may occur. Since min corner is run at highest voltage, it's possible that temperature inversion may not occur at higher voltages, so lowest temp may still still be ok for getting min delay. However, the behaviour may be different for different Vth transistors, so some paths may have min delay at some temp, while others may have at some other temp (depending on the High Vth and Low Vth mix of cells in the path).  So, a set of temperatures should be used at the highest voltage to make sure that all possible extremes of min delay are captured. Here we take R, C at their min values (even though R,C may not be at their min necessarily)

3. max: This is the MAX delay corner where transistors are supposed to be at their minimum delay (i.e fastest). This is just the opposite of MIN corner. So, Process = SS which means NMOS and PMOS are at their slow process value (i.e slow speed), Voltage = Minimum voltage that the design is supposed to be exposed to (maximum PMU voltage undershoot) and Temperature = highest temperature which is taken as +150C. Again there is this temperature inversion and voltage dependency problem as discussed above. Since we are at lowest voltage, Temp inversion is very likely to happen at low voltages, so lowest temp should be used here. So, for both min and max delay corner, we use the lowest Temp corner. Here we take R, C at their max values (even though R,C may not be at their max necessarily)

Temperature turned out to be not so straight forward, at low nm tech. With further scaling to <14nm, the trend with Temp inversion gets even more hotch-potch where depending on the voltage and the Vth of trnasistors (high Vth or low Vth), transistors got fast or slow at lower temperatures. So, now there is no clear trend on what temperatures to use. Best is to run max and min delay corner across a set of temperatures.

Global variation vs local variation:

When we talked about PVT corners above, we assume that same PVT corner applies to all transistors on a single die. For a different die, different PVT corner would apply. Assumption is that across multiple wafers and multiple dies on each wafer, all dies would be bounded by the max and min PVT corners. So, when we run STA at the max and min corners, we have kind of guaranteed that timing will be met for all these dies, no matter what the process, voltage or temperature be. So, if Process is fast, Voltage is low, and Temperature is high, this particular PVT point is bounded by our our max and min PVT corner, and so will pass timing as long as max and min timing are passing.

However, a question that immediately comes to mind is what about the PVT variations across multiple transistors within a die. For ex, on a given die, not all transistors will be fast-fast at same speed. They will have local variations, and some transistors will be slower than that "fast" corner, while some might be even faster. Similarly for voltage, not all transistors on the same die will see exactly the same voltage. Some transistors may see a little higher voltage while some others might see a little lower voltage depending on IR  drop. The same goes for temperature. Since temperature of a transistor is heavily affected by it's surroundings, it's possible that some transistors which are ON most of the time and running at high frequency may see a higher temperature than some other transistors which are OFF most of the times. This will affect delay of transistors differently and depending on the path, the timing will need to be re calculated with these more precise values of PVT. This is called on chip variation (OCV). This will be discussed in "OCV section".

What if we don't want to deal with OCV, since we have no clue on how to measure these PVT variations within a die. In that case we could use "max corner" for 1 path and min corner for other path on the same die. This guarantees that our chip will meet timing no matter what. However this is way pessimistic that what a real silicon would see. So, we end up unnecessarily putting a lot of margin in design which wastes area and power. We'll study about all of these in "OCV section", which is the next one.

Details

Published: Wednesday, 20 January 2021 19:00

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VLSI Introduction:

VLSI: Very Large Scale Integration. This is the field of Electrical/Electronic Engineering that deals with the science of designing circuits and building them on chips.

There are many preliminary courses that you will need to take, before you can start designing chips.

Circuits are built using passive components: R, L, C.

On top of above 3, we have an active component known as "transistor" that brought about all the revolution in electronics. Transistor is basically an "electronic switch" that you can turn ON or OFF using voltage signal (by contrast, a manual switch at home requires physical force to turn it on or off). When we talk about VLSI or solid state, we are almost exclusively talking about transistors. Transistors are what made all modern chips possible, so it's one of the greatest invention that gave us all modern electronics today.

VLSI History:

Since 1950's, all these passive elements used to be stand alone devices. They were big, and to make any circuit out of them required considerable space. Then came active element, transistors. Transistors used to be stand alone devices too, similar to Resistors and capacitors. However, researchers started looking into ways of making these transistors smaller and getting a lot of them to be etched out on a single base. Silicon became a compound of choice. This gave birth to LSI in 1950's.  With advent of LSI, we started building transistors on Silicon wafers and integrating a lot of them on the same silicon wafer. This greatly reduced the size of each transistors and allowed thousands of transistors to be put together close to each other connected by miniature wires which were themselves etched on silicon. The number of transistors being etched on a single wafer kept on increasing which gave birth to VLSI. A very good history of VLSI and how small the dimensions of these transistor were in each technology can be found on this link:

https://en.wikichip.org/wiki/technology_node

FEOL vs BEOL:

FEOL (Front End of Line) refers to steps associated with transistor fabrication. Transistor fabrication on silicon involves 10-50 steps for modern CMOS tech. It needs the most advanced and cutting edge tools and tech to build the smallest transistors. It takes 30 days or more to complete all fab steps associated with a transistor and get it out. Photomasks for transistors are also the most expensive ones, as they need to have very high accuracy for the small size of the transistors.

BEOL (Back End of Line) refers to steps associated after the transistors layers are done. This is where interconnects to transistors are built using metal layers. Fabricating these metal layers isn't as complex as fabricating the transistors. Once transistor layers are deposited properly and transistors are functioning, building metal layers on top of it goes faster. It's 2 masks for each metal layer (one for horizontal connection and other for vertical cuts to connect one layer to another). These masks are cheaper as the width of metal layers isn't as small as transistor gate length. Each metal layer takes a day to go thru the fab, so 10 metal layers will take about 10 days. As FEOL dimensions shrink, BEOL dimensions also need to shrink, so that the overall gain in density can be achieved.

Full node (FN) vs Half node (HN):

Transistors size can get reduced by any amount from one node to other. However, it would be very expensive to introduce a new node just for little bit of size reduction. Reason is that size reduction of transistors usually imply that associated tools used in Fab have to be changed to design with lower transistor size, which is very costly. A rule that has been followed in Semiconductor fabrication is that a transistor reduction that would give 2X the transistors density is worth the cost. The lower size of chip due to 2X the density implies chip cost has been cut into half, which is able to absorb the extra cost of fab retooling. To get to 2X density, both X and Y dimension of chip has to decrease by 0.7X (since 0.7X * 0.7y = 0.5xy => half the size of original chip). So, we not only reduce the length of transistor by 0.7X, but we also decrease the width of transistor by 0.7X. This is known as a full node.So going from 1um node to 0.um node is a full node transition which is very costly. Full node transistion has been happening every 2 years, implying transistor density is doubling every 2 years. This is also known as Gordon Moore's Law, who famously predicted this in 1965. However, companied don't want to sit idle for 2 full years, without showing any improvement. To address this, these chip companies introduced a half node. Half node is a 10% reduction in size of transistors in fab without changing the tools completely. Design was done in such a way that existing design could be used, and reduction in size was done entirely in fab. This gave some incremental improvement without redesigning the circuit or re-tooling the fab. This came to be known as half node and came in between 2 full nodes. So, a half node would give 20% (since 0.9X * 0.9y = 0.8xy) reduction in IC size, while full node would give 50% reduction in size.

Every 4 years, we would get transistor length reduction to be 1/2 of it's current one (since every 2 years, it goes down by 0.7X, so every 4 years it's 0.7*0.7=0.49 or almost half). That is why FN tech goes like this 1um -> 500nm ->  250nm -> 130nm -> 65nm -> 32nm -> 16nm -> 7nm -> 3nm, and so on.

Tech Node:

A technology node of certian um or nm usually refers to the smallest dimension that can be etched out on the silicon. Usually it's the gate length of the transistor that has the smallest dimension. Also, the gate length of a transistor has inverse relationship to the performance, as shorter transistor length implies a higher current, and hence faster speed. Since the transistors were invented, tech nodes referred to transistor length (so a 2um node meant that the transistors on this node have 2um gate length with slight variations. You can't etch out a gate with length < 2um on this node). Along with this we also got a 2X increase in density with every full node. But as we got to smaller transistor lengths, it was observed that just reducing transistor gate length didn't guarantee a 2X increase in density. It was limited by how much closer you could place transistors to each other. If you couldn't scale that distance to half every 2 years, you wouldn't get to 2X scaling. So, 2X density improvement became the new definition for defining a full node. The nm or um number for tech node that used to refer to gate length didn't necessarily refer to gate length anymore, though it's close. Some people starting calling the half pitch as the better  definition for a tech node. Pitch is defined as the distance between 2 adjacent gates. Min pitch refers to the closest you can get 2 gates to each other while still having space to make contacts to both the gates and the active source/drain regions. Half pitch is half of this distance, and turns out that half pitch is a very relevant number when talking about density improvement. So, a lot of later tech nodes since 2000 use their tech node "nm" to refer to the "half pitch" or "gate length" or to something smaller than both of these. That "nm" number is more of a marketing ploy now. So, keep that in mind when going thru the tech nodes below.

Tech node timeframe is as below. I'm showing full node process only.

• 50um - 10um => 50um was the first process developed in mid 1960's for building transistors on wafers. The typical wafer size (diameter) was < 1 inch (only 22mm). 50um is the typical thickness of human hair (100um is 1/10th of a mm), so transistors of this size could possibly be seen by naked human eyes (though microscope will be necessary as these 50um lines will be very close to each other and hence difficult to distinguish). Going from 50um to 10um, wafer size increased to 2 inch. 10um was being developed actively during early 1970's. Intel' 8008 was developed on 10um tech.
• 10um - 1um => From mid 1970's to late 1980's, transistor size kept on decreasing, while wafer size kept on increasing (from 1 inch all the way to 6 inch or 150mm), resulting in even greater transistors per wafer. Bulk CMOS tech was being used with voltages at 5V. Only one metal layer was being used for interconnect, though 2 metal layers started getting used for 2um or below.. Intel's 8086 series was being developed during this time using 1 tech nodes close to 1um.
• 1 um => introduced in late 1980's. Intel's 80386 and 80486 were based off this. 1um tech was big step, as transistors of this size were considered infeasible just a decade or two back.
• 700 nm => Introduced in early 1990's, it was a full node followup to 1um tech. 3 metal layers were being used here. Intel's Pentium Pro was built on this process node.
• 500 nm => Commercial ICs started getting produced using 0.5um tech in 1993. It was called a half micron process. 4 metal layers of Al-Cu (Aluminum Copper) started getting used. Oxide thickness was reduced to about 10nm. The process typically had a Threshold voltage of 0.5V and a supply voltage of 3.3 V.
• 350 nm => Commercial production using 350nm started in late 1995. Number of metal layers went to 5 with oxide thickness further reduced to 6nm. Intel's Pentium and Pentium II were built on this.
• 250 nm => Also known as "quarter micron" process,  Intel along with other leading semiC companies entered 0.25um process in 1997. Intel's process used 200 mm wafers, SiO2 dielectric and polysilicon electrodes. It used Aluminum inter-connects. Intel also made a smaller chip using 5% shrink to original design rules which used. Gate pitch and interconnect pitch was about 500nm-700nm. 
• 180 nm => This was introduced in 1999 by Intel, TI, IBM and TSMC. Number of metal layers went to 7. Gate pitch and interconnect pitch was about 450nm-500nm. 
• 130 nm => This was introduced in 2001 by Intel, TI, IBM and TSMC. Number of metal layers went to 8. Gate pitch and interconnect pitch was about 350nm. SOI process instead of Bulk started getting used at AMD, IBM, etc which was basically silicon on insulator which allowed the body to float instead of being tied to power supply as in bulk tech.
• 90 nm => This was introduced in 2003. Gate pitch and interconnect pitch was about 250nm. At 90nm, 300 mm (12 inch) wafers started getting used, which was a big step from 200mm or 8 inch wafers that were being used before than.
• 65 nm => This was introduced in 2006. Gate pitch and interconnect pitch was about 200nm. 
• 45 nm => Commercial manufacturing using 45 nm process began in 2007. Intel's 45 nm process was the first time high-k + metal gate transistors was used in high-volume manufacturing process. Before this, poly was being used for gate, which had very high resistivity. Gate pitch and interconnect pitch was about 160nm-180nm. 
• 32nm => 32nm manufacturing began in 2010. Metal layers went to 9 to 11 layers. 193nm Immersion Lithography was being used for 32nm. Gate length was 30nm, even though node was 32nm. Gate pitch and interconnect pitch was about 100nm-130nm. Supply voltages came down to 1V or below for the first time. 28nm was a half node introduced a year later, and was a stop gap b/w 32nm and 22nm.
• 22 nm => 22nm manufacturing for processors began in 2012, although memories were being built on this node since 2008. Until 22nm, we were using planar transistors that were conventional transistors that had been used since CMOS tech came into existence. However, it was becoming more difficult to scale planar transistors as sizes kept on shrinking. Companies were looking for alternatives. Fin based 3D transistors were actively being researched and showed promise. The 22 nm became Intel's first generation of Tri-gate FinFET transistors and the first such transistor on the market. Other companies didn't jump to FinFET bandwagon yet and continued with planar transistors. Intel's core i3, i5 and i7 were built on this new tech. Gate pitch and interconnect pitch was about 80nm-100nm. Supply voltages came further down to 0.7V-0.8V.  20nm was a half node introduced in 2014 followed by a 16nm Full Node in late 2015. 20nm was still in Planar technology while 16nm moved to FinFet.
• 16nm / 14nm => 16nm was the first time industry moved away completely from Planar transistor to FinFet transistors. Things got more confusing as "nm" no longer referred to gate length, and different companies started adopting different naming convention as per their choice. There is also confusion as to whether 16nm or 14 nm is a full node. Based on Maths, looks like 15nm should be full node. Some companies went with 16nm as their full node, while others went with 14nm. Manufacturing using 16nm/14nm began in 2014/2015. Both 14nm and 16nm were still based on 193nm Immersion Lithography. Supply voltages were same around 0.7V.
  
  • 16nm: TSMC introduced their first 16nm FinFet process known as 16FF, followed by later revisions as shown below. Gate length was 34 nm (not 16nm), with Fin pitch at 48nm and Gate pitch at 90nm.
    
    • 16FF => 16nm FinFet process. It used the same 20nm BEOL.
    • 16FF+ => Improved 16nm FF process to give 10-15% perf improvement
    • 16FFC => 16nm FinFet Compact was the refined version of earlier process which reduced cost by using less masks, and used half the power.
  • 14nm: Intel introduced their 14nm process as P1272/P1273. Samsung introduced 14LPE (Low Power Early), 14LPP (Low Power Performance), 14LPC and 14LPU. IBM (Fabs were sold to Global Foundary in 2014) 14HP process started manufacturing a bit later in 2017. UMC also started mass manufacturing of their 14nm process in 2017.  All these had smaller gate length varying from 20nm-30nm (nowhere close to 14nm). Fin pitch was 42nm, while gate pitch was at 70nm-80nm. Minimum metal pitch was 50nm-60nm. Fin width was 8nm, with Fin height at 40nm. Intel 14nm process had further refinements with 14nm+, 14nm++ which yielded up to 50% less power and 30%-40% higher drive current. Intel's 14nm process was the densest, with 1.5X raw logic density when compared to other leading Fabs.
• 14 nm =>
• 10nm
• 7nm
• 5nm
• 3nm
• 2nm

Diff node Scaling:

VLSI Topics:

This is the sequence of topics we'll cover in VLSI section:

1. R, L, C: A lot of simple circuits may be made using R,L and C. These are simple to understand.

2. Solid state devices: Transistors, diodes. These are more difficult to understand.

3. Digital Library cells:

4. Digital Hardware language:

5. CAD tools

6. Analog design

7.

Links:

1. Sunburst: One of the best places to learn digital vlsi design: http://www.sunburst-design.com/

Here they offer a lot of paid training. You don't need to take any paid courses. They do have a lot of free papers, that have a lot of useful info. http://www.sunburst-design.com/papers/

I'll list these papers in different section as we talk about the various topics.

2. Teamvlsi: I saw a few good topics covered here. They also have a youtube channel with good videos. Link: https://teamvlsi.com

3.