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Published: Monday, 03 May 2021 17:22
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Landscaping:

if you buy a standalone house, chances are high that it will have a lawn in the front and in the back. If you are buying a condo, lawn care is taken care of by the HOA (Home owner Association). If you are buying a townhome, you may have to take care of the small lawn (if any), depending on the specific HOA.

Lawn care requires considerable time and money. If you are buying a brand new house, it will come with the lawn setup with grass and small plants and trees. You will immediately see 2 kind of areas: one with grass, while the other with no grass, but having cut wood (known as mulch). This mulch area is around trees and plants, so that no grass grows in that area. It's just to give a better appearance to the lawn.

If you buy a house in USA which is part of an association, then one of the long lasting nightmares as a homeowner are the landscaping violations. The whole and sole reason HOA  exist is to make sure that can fine home owners if they don't like the landscaping of that particular home. This is easy and recurring money stream for the management company which manages the HOA (as half of the fines go to mgmt Co). All other fines are very objective, can be contested easily and are one time fix. On the other hand, landscaping rules are very obscure (something like "landscaping has to be maintained in a first class condition"), can be sent out weekly, and for any reason (weeds in yard, grass on mulch, dead plants after winter, not enough green color to grass, blah blah, basically anything you can dream of ...)

No matter how much you maintain your yard, management company will always find a way to send you a violation notice. They will start imposing fines, interest, etc, and there is little respite from this. In the past, HOAs have spent hundreds of thousands of dollars filing lawsuits over landscaping, and have successfully foreclosed homes, which is totally illegal and non sense. Many HOA just fine you when they come to know that you haven't hired a professional to maintain your yard. Best thing is to avoid buying a home in an HOA. However no new homes in USA come without an HOA, so you are stuck.

Maintaining landscaping is one thing, and not getting fines is another thing. You can spend a lot of money and time trying to avoid HOA fines related to landscaping. I don't know when will that suffice. My article below lists general tips and tricks to maintain your landscaping in a decent condition. This will save you money, and require as little of your time as possible.

 My goal is to never spend more than $1K/year on landscaping including all the costs as irrigation, mowing, yard supplies, machines, etc.

 

 

 

Grass types: 

There are different kind of grass that builders put in your yard. You have to know your grass type, as certain fertilizers, weed killers, etc only work with certain grass type. If you put the ones that are nt meant for your grass, they can damage your grass seriously. In Texas, these are the 2 grass types that are most common

  1. Bermuda grass: This is the thin grass that is the most common one that in see in mst of the yards. Builders prefer this grass as it's cheaper. Also, their roots grow and expand making a mesh, which allows dead spots to be filled in very easily, w/o requiring you to resod grass. So, economical too. My yard in Texas has Bermuda grass.
  2. St Augustine grass: This is the thick grass type. It's less common, as it's expensive. Also, their roots are limited to where the grass is, so if the grass dies, then those dead spots won't be filled by roots of nearby grass. But they are more heat resistant, so will likely survive hot summers with less water.

 

 

Mowing: 

The very first thing that you will need to do is mow the lawn. This means cutting the grass, preferably every 2 weeks during summer and every 4 weeks during winter. I personally felt that mowing it every week, keeps it much healthier and it takes less time to do it. Regular mowing creates a tillering effect, keeping your grass greener and softer. You will need to buy a lawn mower to do this.

There are 3 different kind of lawn mowers to do this job:

  1. Manual mowers: These require manual effort, as the cutting blades rotate as you move the mower. It's the cheapest option, but takes lot of your energy. Good to exercise, but I don't see these anymore.
  2. Gas mowers: These run on petrol, and maintainance is required on regular basis. Cost in the range of $100-$200.
  3. Electric mowers: These mowers are the most convenient, as they run on electricity. Two options are available here: one with electric cords (corded), and ones without (cordless). Cordless ones have rechargeable battery, so they are heavier than corded ones. But advantage is that there is no cord to buy, and no cord to maneouver around. However, cordless mowers will last for an hour or so in one charge, depending on the battery life, so your lawn has to be less than 10,000 sq ft, or else it's going to require multiple charging in order to complete one mowing. Price wise corded mowers are cheaper than cordless ones. However, if you shop around, you can find cordless mowers for under $300 with good 2 year warranty. Do NOT buy a corded mower as those are difficult to manage, regularly gets the cord cut, and eventually don't end up saving any money. Buy the cordless one. 

Mower deals:

Tips for mowing:

  1. Always leave 3 inches of grass height in the lawn. you can do this by adjusting the height of the mower to 3 inches. Reason for leaving 3 inches is this => grass has 2 parts, a bottom dry part, and the top crown. you want to cut only the top crown. you don't want to cut bottom dry part, as that part retains mositure, and cutting it make make much harder for grass to grow again.
  2. Never cut more than 1/3rd of the grass height in one mowing. If you've to cut more than this, wait for 2-3 days, and then cut again, 1/3rd of remaining grass height. This way, grass is healthier.

Mowing is just one lawn care activity. It doesn't prevent the unwanted plants (weeds) from growing. These weeds will grow along with your grass, and start killing your grass, as they take away the necessary resources (water, sunlight) from the grass for their own growth. For these, we need fertilizers and chemical spray. This is covered under next section.

 

 

Weed Control:

Weed Control is best done before weeds grow. Crabgrass is the most common weed that is hard to pull out, and grows very fast. Below are few chemicals that help prevent crabgrass as well as other weeds.

Crabgrass Control (Weeds): https://www.lowes.com/pd/Scotts-32-04-lb-Crabgrass-Control/1000140423

Pre Emergent: These are chemicals that you spray before the weeds come, i.e when weeds are dormant. This is usually in the fall (i.e Nov-Feb). If you spray pre emergent during the fall, you will hardly see any weeds during the summer. If you forget to do this, then it's very hard to control the weeds with post emergents or other chemicals. It's too late by the time you start seeing weeds germinate.

Crabgrass pre-emergent: Crabgrass is pretty easy to control. You just have to put the right chemical/weed killer, else it's impossible to get rid of it. Regular weed killer will work on all other weeds, but will never work on Crabgrass. A chemical, Prodiamine, is very effective. Here's a link: https://www.amazon.com/Quali-Pro-Prodiamine-Pre-Emergent-Herbicide-Granules/dp/B004GTQBEK

Prodiamine Preemergent => It's expensive at $100, however it will last you 10 years or more. Don't buy smaller bottles, as they cost you way more over the long run. This is the way to apply it:

  1. Measure your yard area. Per 1000 sq ft, you need 0.5oz of Prodiamine. The dosage of prodiamine determines how long the yard is going to be crabgrass free. For 4-6 months protection, 0.5 oz is good. For 12 month protection, you need 1 oz per 1000 sq ft. Don't go over 1oz per 1000 sq ft, as that may damage the grass.
  2. Fill in 1 gallon water in the spray tank. 1 gallon is for 2000 sq ft of yard area. Put in 1oz  - 2oz of Prodiamine in it. Shake it well. This amount in spray tank is good enough for 2000 sq ft of yard area. For 4000 sq ft of yard area, repeat twice.
  3. Once the water and the Prodiamine are mixed in the tank, start walking over the yard, spraying it. Within 14 days, turn on your sprinkler system to let this chemical get into your soil. This will have more effective control of weeds.

 Post Emergent: These are chemicals that you spray after the weeds come, i.e when weeds are visible. Most of the weed n feed fertilizers, weed killers, etc you see in the market are the post emergent. These are not as effective as Pre emergents. You need to apply post emergent in conjunction with Pre emergent to get best results. If you have done a good job applying Pre-emergents, you won't need much of post emergents,

 

Grubs: If you see your grass not needing a cut even during active growing season of summer, that means the grass isn't growing, which indicates something wrong with the grass. Most of the times, you will also see that the grass is really easy to pull off from certain places (sometimes it comes out like a carpet indicating no roots at all). The most common reason for this is over abundance of grubs in your soil, which are little worms in soil, which feed on root of any plant including grass. If you are seeing the damage, it's too late as larva of Grubshave already hatched into adults and will keep eating grass. You can control further damage by killing whatever grubs you have by using this 24 hr Grub Killer product => https://www.amazon.com/BioAdvanced/dp/B001H1GQ54

For next season, you should apply grub killer to prevent grubs from laying eggs. This is done in Spring season before summer comes (i.e March/April). So, we kill Grubs before they lay eggs. You need to water extensively to let this chemical go underneath deep in the soil to get all grubs. You need to apply only once a year, as after summer, no grubs will come anyway. You need season long Grub control for this => https://www.amazon.com/Scotts-GrubEx1-Season-Long-Killer/dp/B0050DV4ZW/145-1063152-0610042

 

 

Sprinkler Installation and Repair:

If you have a sprinkler system to water your lawn, it's another financial pain. However, you should be able to do almost every repair yourself, instead of spending 100's of $ for each call. They don't involve any plumbing or fixing difficult leaks, as most of the parts are standard, and may just be switched with a new one. Repairing sprinklers is NOT plumbing job, small leaks here and there may still be OK and NOT that difficult to fix :)

If you dont't have a sprinkler system (especially for old houses), I would suggest to not put one, as it not only saves money, but there's also nothing to maintain. Just use a regular garden hose to water your yard from time to time. Grass may die in extreme summer, but will come back when the weather cools. Just don't allow grass to die to a point where roots start dying. Then, grass won't grow again. Water the lawn before that starts happening. 

First, let's understand the basics of how sprinker system works:

Link showing mock setup=> https://www.youtube.com/watch?v=vYV7Oac5T98

Link showing installation from scratch => https://www.youtube.com/watch?v=GMsVext_DnY

Pipe size:

There is a pvc pipe running under your yard soil, that carries water to all sprinkler head. Pipes are classified based on internal diameter of the pipe. External diameter doesn't matter for fittings. Most of the pipes used in homes are either 1/2 inch pipes or 3/4 inch pipes in internal diameter. The next size up is 1 inch pipe which are mostly used in industrial agriculture, but not in residential yards. You have to know your pipe size.

You have a solenoid, as well as water heads that may go wrong. Lastly, you may have the sprinkler board

Changing Sprinkler heads:

One of the easiest things to do is changing sprinkler heads, They my break, leak, or just not work efficiently after a couple of years. Very easy to replace and each head costs only $5-$10 depending on whether's it's stationary (where head doesn't rotate) or rotary (where head rotates in an angle, and angle is adjustable).

Video explaining how to change heads: https://www.youtube.com/watch?v=c6BDhysSi3A

 

Repair Pipe cuts:

Sprinkler pipes may get cracks,leak or may just accidently get cut while you are diffing in the yard. It's very easy to fix. Tough part is finding out where the leak is. Since it's under the yard, there are multiple ways to find the leak. One is to turn off all faucets, taps in your house, and see if your water meter needle is still moving. That may indicate a leak in the main line before it enters the sprinkler. Sprinkler pipe leaks may not be caught using this process as sprinkler is turned off by the sprinkler board.

To find sprinkler pipe leaks, turn on the sprinkler in manual mode, and check for low water pressure (i.e if not all sprinkler heads come up, that may be a problem with sprinkler head, solenoid or some leak in the pvc pipe for that zone). Rule out the sprinkler head problem by replacing the heads not popping up with new ones. If they still don't pop up, replace the solenoid, and if still doesn't pop up, then chances are there is a leak. Look for water pooling in any certain area, or grass being overly green in same patch of ground. That indicates that patch of grass is getting lot more water underground which can only happen with underground leak.

Once you have dug up, and found the cracked pipe, there are 2 ways to fix it:

 

 

Misc supplies/tools:

Water hose:

You will most likely need a hose to water your grass or your plants at some point. May be because sprinkler stops working, or you might just want to water your grass  little extra. 100 ft hoses with lifetime warranty are available for $50. Buy these. Do NOT buy the "expandable hoses" as they are not going to last beyond one year. They are fancy but that's all they have.

05/25/2025 : 100 ft garden hose => https://slickdeals.net/f/18331678-flexzilla-garden-hose-5-8-in-x-100-ft-heavy-duty-lightweight-durable-zillagreen-hfzg5100yw-e-55-33-at-amazon

Though the link above takes you t amazon, you can buy the same hose from home Depot for the same price => https://www.homedepot.com/p/Flexzilla-5-8-in-x-100-ft-ZillaGreen-Garden-Hose-with-3-4-in-GHT-Fittings-HFZG5100YW-E/203549988

 

 

 

 

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Published: Tuesday, 23 March 2021 22:55
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PCI Bus:

PCI is a 2nd generation bus standard that was developed by Intel in 1990. By 1994, PCI became widely used in Pentium PCs. PCI-X which was an enhanced version of PCI was released with faster speeds. After PCI and PCI-X, came the enhanced PCI Express (or PCIE) which was the 3rd generation bus standard, with much faster speeds. This is what we have today in all modern devices. Original PCI and PCI-X are almost non existent.

There were multiple PCI standard as PCI 1.0 (5V signaling), PCI 2.0 (3.3V signaling, PCI-X) and PCI 3.0 (PCIE).The 2nd generation buses were PCI and enhanced version of PCI called PCI-X. The third generation of PCI is what we have today known as PCI Express (or PCIE). We'll look at 3 standards: PCI, PCI-X and PCI Express. like any other bus standard, PCI main objective is to transfer data between devices at highest rate possible.

Spec:

PCI 1.0: PCI bus originally had 33.33MHz clock with synchronous transfers. They had 32 bit wide bus, which gives it a peak transfer rate of 4byte*33.33=133MB/sec. It's 5V signalling, though 3.3V is also supported. It allowed multiple devices to share the same bus, which put a limit on the maximum frequency the bus can support. Clock speed of 33.33MHz (i.e time period=30ns) was only able to support 4-5 slots per bus, as beyond that load would be too high to meet timing. PCI later increased clock speed to 66MHz, which allowed only 1-2 slots per bus.

PCI 2.0: Later PCI-X came with 66MHz and 133MHz clock speeds, with more slots per bus.

PCI connector:

There are PCI connector cards which have contacts on each side of the connector. They have few notches to make sure that they fit only where they are compatible with the voltage supply (5V or 3.3V).

PCI bus transactions:

PCI bus traffic consists of a series of PCI bus transactions. Each transaction consists of an address phase followed by one or more data phases. The direction of the data phases may be from initiator to target (write transaction) or vice versa (read transaction), but all of the data phases must be in the same direction. Either party may pause or halt the data phases at any point.

Each PCI bus transaction

 

a local computer bus that attaches hardware devices in a

PCI Express:

Documents:

This by mindshare is a good one:

https://www.mindshare.com/files/resources/MindShare_Intro_to_PIPE_spec.pdf

 

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Published: Wednesday, 17 February 2021 21:04
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Genus:

Genus is the latest Synthesis tool from Cadence released somewhere around 2015. Before that RC (RTL Compiler) was the Synthesis tool from Cadence. Genus supposedly has better correlation with PnR and Timing tools from Cadence, as some of the engines that are used in those tools are used over here in Genus.

Legacy Vs CUI mode:

Genus uses CUI mode by default. Below are some diff b/w DC and Genus cmds:

DC Command
Genus Command
Notes
get_attribute get_property Most of DC "attribute" cmds have corresponding "property" cmds in Genus.
define_user_attribute define_attribute Other Cadence tools (Innovus/Tempus) use define_property (as expected), but surprisingly Genus doesn't support this, it has its own different define_attribute instead.
list_attributes list_property Genus. Tempus and Innovus all use list_property
set_user_attribute set_attribute Again, Genus uses "attribute" instead of "property". Here the argument order is different than in DC, objects need to come last in Genus
alias alias alias A B C works for DC but should be alias A "B C" for Genus. only double quote. Single quote doesn't work
report_path_group report_timing -cost_group * path group doesn't have a separate cmd in Genus
set_path_margin set_path_adjust  
get_cells, get_net, get_pins, get_lib_cells get_cells, get_net, get_pins, get_lib_cells same as DC (these are SDC cmds)
remove_designs * delete_obj /designs/* Genus has virtual linux style dir structure
read_verilog read_netlist same as DC
current_design Itop current_Design Itop same as DC
report_timing report_timing same as DC (these are SDC cmds)
set_false_path, set_multicycle_path, set_case_analysis, .. set_false_path, set_multicycle_path, set_case_analysis, .. same as DC (these are SDC cmds)
     
 SDC cmds are partially supported in genus.
Genus help:
On genus shell, type "help cmd_name" or "man cmd_name" and it will show the details of the cmd. Also, partial cmd name as "help *lib*" will show all cmds with lib in the name. Typing first few letters of cmd followed by a tab shows all possible cmds starting with those letters.
-------

Genus flow:

It's same flow as RC.

run Genus: script run.tcl

LEGACY MODE: genus -legacy_ui -f tcl/run.tcl -log /logs/top.log => prompt shows as genus@root:>

CUI MODE: genus -f tcl/run.tcl -log /logs/top.log => prompt shows as legacy_genus :/>

NOTE: Now you can use genus cmds on prompt. To see gui, type gui_show. (See section on "Cadence cmds" for details on CUI vs Legacy).

 

 

Steps:

1. Read Tech libs:

The default search path for libraries, scripts, and HDL files is the directory in which Genus is invoked. To specify non default path for library, set following attributes:

set_db lib_search_path

 

2. Read RTL:

3. elaborate => converts HDL rep into a netlist and performs High Level Opt (HLO). HLO here include Mux optimizations and Spasreness and redundancy opt

4. Read UPF, Timing constraints, DEF => UPF needs to be read only if there are multiple power domains in the design.

5. syn_gen => synthesize to generic gates. Performs data path and other HLO. Also does Mux opt, bit level opt, generic placer and physical buffering

6. syn_map => maps generic gates to tech gates. Does datapath arch selection, DP opt, Bit level opt, tech mapping, multibit opt and Timing/area CRR

7. syn_opt => performs bit level opt for area and timing

8. scan

9. syn_opt / iSpatial / Congestion prediction =>

 

Flow:

Clock cmds:

  • report_clocks => SDC cmd, uniform syntax
  • report_clock_gating => Reports clock-gating (CG) information for the design, and is useful to see all the statistics on where clk gating is not effectively applied.
    • report_clock_gating > clk_gating.rpt => This shows summarized info for # of CG (Genus vs Non-Genus), # of flops (Genus vs NonGenus gated/ungated), MultiBit Flops, etc. It reports # of leaf CG instances, followed by the # of Multi Stage CG (MSCG) instances (i.e where CG are NOT leaf CG anymore). MSCG has 2 options to indicate where should it cout from => from the flop or from the root.
      • -multi_stage_count_from_flop => this option counts from leaf flop, in which case Level 0 is the CG driving the flop, Level 1 is one level higher and so on.
      • -multi_stage_count_from_root => this other option is for counting from the root clk pin, in which case Level 1 is the top level of CG, level 2 is next lower level, until we get to the flop. NOTE: Here levels start from Level 0, while when counting from flop, we started with Level 1.
  • report_clock _tree_structure -out_file clks.rpt => This reports the clk tree hierarchy, which is very useful to see the whole clk tree structure. It shows different LEVELS of clk tree as L1, L2, etc. Start of a new level is determined if there is a clk gater, RTL instantiated gate, etc in design (i.e anything other than buffer and inverter, unless it's RTL instantiated buf/inv). There are many options to fine tune this report.
    • report_clock_tree_structure -show_sinks -clock_trees {clk1 clk2} => By default cmd shows the clk tree for all clks until the sink. These options show clk tree only for specified clks, with sinks included. NOTE: the same flops may appear under multiple clks, since 1 flop may be driven by multiple clks (depending on clk sdc file)
  • report

 

Details
Published: Thursday, 04 February 2021 01:41
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CPF Syntax:

CPF is very similar to UPF in syntax. Since it's not used widely anymore, I'm listing an example below which shows the basic syntax. You can omit this whole section on CPF.

CPF cmd file Example:

Below is an example CPF file. The top level file is called TOP.cpf.

TOP.cpf =>

set_cpf_version 1.1
set_hierarchy_separator "/"
set_design chip_tb/chip_top/u_dig_top_wrapper/u_dig_top

##create top level PD
create_power_domain -name PD_TOP \
     -default => includes everything in PD_TOP that isn't included explicitly in other domains

##create PD for all domains
#for PDMCU ( pdmcu = u_imp in arm_core + others attached to mcu),
create_power_domain -name PD_MCU \
     -base_domains { PD_TOP } \
     -instances { \
           u_dig_top_pdmcu/u_ahb_to_apb u_ahb_peripheral_system u_dft u_sync_2s \
           u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp } \     
     -shutoff_condition {!u_pmu_top/dig0_pm_if_ps_on | !u_pmu_top/dig0_pm_if_ps_good} => Anytime these signals are 0, all o/p ports of above instances goto "x", when running RTL sims with this cpf file (power aware rtl sims).

#similarly for other PD (PD_HFADC)
create_power_domain -name PD_HFADC \
     -base_domains { PD_TOP } \
     -instances { u_apb_peripheral_system/u_dig_adc/x_adc_hf } \
     -shutoff_condition {!u_pmu_top/dig1_pm_if.ps_on | !u_pmu_top/dig1_pm_if.ps_good}

#PD for RAM/ROM IP do not have inst name, since they are mapped later with their cpf file
create_power_domain -name VD_RAM_MTB \
     -base_domains { PD_TOP } \
   -shutoff_condition { !(u_dig_top_wrapper/u_ram/PON&u_dig_top_wrap/u_ram/PGOOD) }


#####################
##create power nets
#primary voltage
create_ground_nets -nets { VSS }
create_power_nets  -nets { VDD   } -voltage 1.08

#switched voltages
create_power_nets -nets { VDD_mcu   } -voltage 1.08 -internal
create_power_nets -nets { VDD_hfadc } -voltage 1.08 -internal

update_power_domain -name PD_TOP \
     -primary_power_net VDD \
     -primary_ground_net VSS

update_power_domain -name PD_MCU \
     -primary_power_net VDD_mcu \
     -primary_ground_net VSS

update_power_domain -name PD_HFADC \
     -primary_power_net VDD_hfadc \
     -primary_ground_net VSS

#create connections
#create pins for PDTOP aand connect it appr
create_global_connection -net VDD -pins { VDDNW }  -domain {PD_TOP}
create_global_connection -net VDD -pins { VDD } -domain {PD_TOP}
create_global_connection -net VDD -pins { VDDC } -domain {PD_TOP}
create_global_connection -net VDDAR -pins { VDDAR } -domain {PD_TOP}
create_global_connection -net VDD -pins { VDDPR } -domain {PD_TOP}
create_global_connection -net VNWA -pins { VNWA } -domain {PD_TOP}
create_global_connection -net VDDS -pins { VDDS } -domain {PD_TOP}
create_global_connection -net VPP -pins { VPP }  -domain {PD_TOP}

#similarly do it for PD_MCU and PD_HFADC
create_global_connection -net VDD_mcu -pins { VDDNW } -domain {PD_MCU}
create_global_connection -net VDD_mcu -pins { VDD } -domain {PD_MCU}
create_global_connection -net VDD -pins { VDDC } -domain {PD_MCU}
create_global_connection -net VDDAR -pins { VDDAR } -domain {PD_MCU}
create_global_connection -net VDD_mcu -pins { VDDPR } -domain {PD_MCU}
create_global_connection -net VNWA -pins { VNWA } -domain {PD_MCU}
create_global_connection -net VDDS -pins { VDDS } -domain {PD_MCU}


#create_global_connection -net VPP -pins { VPP } -domain PD_MCU => for efuse, not needed

#connect switch instances for both MCU and HFADC. Note: RTL for these switches don't have power ports, so we create power pins using this and then connect to allow it to have power aware behaviour. Only Pon, Pgood i/p pins, and ack o/p pins are in RTL of switches.
create_global_connection -net VDD_mcu -pins { VDD }     -instances { u_dig_top/u_sw200u_mcu }
create_global_connection -net VDD     -pins { VDDC}     -instances { u_dig_top/u_sw200u_mcu }

#connect RAM IP pins
create_global_connection -net VNWA -pins { VNWA } -instances {digtop/../u_RAM }
create_global_connection -net VPP  -pins { VPP } -instances {digtop/../u_RAM } => and so on for all power pins


##############
#RAMS/ROMS which have inbuilt support for power switch/isolation. They have separate cpf file which specifies power domain, iso rules etc. See below for such an ex:
-----------------
MY_RAM.cpf

set_macro_model MY_RAM => macro model names as something

# create_nominal_condition -name ON -voltage 0.75 -ground_voltage 0
create_nominal_condition -name ON -voltage 1.08 -ground_voltage 0
create_nominal_condition -name OFF -voltage 0 -ground_voltage 0 -state off

# 3 separate power domains with ports on specified power domains
create_power_domain -name PD_VDDPR_VSS -boundary_ports { FDI FCLRZ PGOOD AON \
    PON RETON SO1 SO0 FCLK OFFP AGOOD FDO RETGOOD Q[31:0] } -default => default, so everything within module is in this PD
create_power_domain -name PD_VDDP_VSS -boundary_ports { ATPGM EZ TM WZ DFT CLK \
    TEZ  WRENZ[31:0] } -shutoff_condition { !(PON&PGOOD) } -base_domains { PD_VDDPR_VSS } => This is swiched PD
create_power_domain -name PD_VDDAR_VSS

create_isolation_rule -name ISOLATION -isolation_output low \
                -from PD_VDDP_VSS -secondary_domain PD_VDDPR_VSS \
                -isolation_condition { !(PON&PGOOD) } \
                -pins {  SO1 SO0 Q[31:0] }

update_power_domain -name PD_VDDPR_VSS -primary_power_net VDDPR    -primary_ground_net VSS
update_power_domain -name PD_VDDP_VSS  -primary_power_net VDDP     -primary_ground_net VSS
update_power_domain -name PD_VDDAR_VSS -primary_power_net VDDAR    -primary_ground_net VSS

create_power_mode -name NORMAL -default -domain_conditions { PD_VDDPR_VSS@ON \
    PD_VDDP_VSS@ON PD_VDDAR_VSS@ON}
create_power_mode -name RETENTION -domain_conditions { PD_VDDPR_VSS@ON \
    PD_VDDP_VSS@OFF PD_VDDAR_VSS@ON}
create_power_mode -name POWER_DOWN -domain_conditions { PD_VDDPR_VSS@OFF \
    PD_VDDP_VSS@OFF PD_VDDAR_VSS@OFF }

end_macro_model
------------------
#now we map above cpf file with IP inst below
set_instance u_dig_top_wrapper/u_dig_top/u_dig_top_pdmcu/u_mica_mtbram/u_ram \
   -domain_mapping { {PD_VDDAR_VSS PD_VDDAR} {PD_VDDPR_VSS PD_TOP} {PD_VDDP_VSS VD_RAM_MTB} } \
-port_mapping { {PON u_dig_top_wrapper/u_dig_top/u_dig_top_pdmcu/u_mica_mtbram/u_ram/PON} {PGOOD u_dig_top_wrapper/u_dig_top/u_dig_top_pdmcu/u_mica_mtbram/u_ram/PGOOD} } \ => maps ports on IP to those in PD domain, needed only if port names differ
   -model MY_RAM => name of model in above cpf file


###############
##power switch rules
#PD_MCU
create_power_switch_rule -name ps_rule_1 \
     -domain PD_MCU \
     -external_power_net VDD

update_power_switch_rule -name ps_rule_1 \
     -prefix ps1_  \
   -enable_condition_1     u_pmu_top/dig0_pm_if.ps_on \
   -acknowledge_receiver_1 u_pmu_top/dig0_pm_if.ps_on_ack \ => these provide ack signals for PA RTL sims. Needed so that state m/c can move forward, if it's waiting for ack signal.
   -enable_condition_2     u_pmu_top/dig0_pm_if.ps_good \
   -acknowledge_receiver_2 u_pmu_top/dig0_pm_if.ps_good_ack

#PD_HFADC
create_power_switch_rule -name ps_rule_2 \
     -domain PD_HFADC \
     -external_power_net VDD

update_power_switch_rule -name ps_rule_2 \
     -prefix ps2_  \
   -enable_condition_1     u_pmu_top/dig1_pm_if.ps_on \
   -acknowledge_receiver_1 u_pmu_top/dig1_pm_if.ps_on_ack \
   -enable_condition_2     u_pmu_top/dig1_pm_if.ps_good \
   -acknowledge_receiver_2 u_pmu_top/dig1_pm_if.ps_good_ack

## isolation rules
#PD_MCU for o/p=High
create_isolation_rule -name iso_rule_high_1 \
     -from { PD_MCU } => apply iso high cells to only 2 pins below
         -pins { u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp/SLEEPING \
                 u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp/SLEEPDEEP \
          }    \
     -isolation_output high \
         -isolation_condition u_pmu_top/dig0_pm_if.iso_enable \ => These iso rules needed for PA RTL sims, so that o/p ports get correct values, instead of "x". NOTE: internal signals of powered dwn blocks will still be x.
         -isolation_target from  \
         -exclude {}

update_isolation_rules -names { iso_rule_high_1 } \
         -location from \
         -within_hierarchy u_dig_top_pdmcu \
         -prefix ISO1_HIGH_

#PD_MCU for all remianing o/p=low
create_isolation_rule -name iso_rule_3 \
         -from { PD_MCU } -to { PD_TOP PD_HFADC VD_RAM } \ => Only apply iso low cells to o/p signals going from PD_MCU to PD_TOP etc, except SLEEPING and SLEEPDEEP o/p signal. All other o/p signals are w/o iso cells.
         -isolation_output low \
         -isolation_condition u_pmu_top/dig0_pm_if.iso_enable \
         -isolation_target from  \
         -exclude { u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp/SLEEPING \
                    u_dig_top_pdmcu/u_cm0plus_subsystem/u_cm0pmtbintegration/u_cm0pintegration/u_imp/SLEEPDEEP \
                  }                              

update_isolation_rules -names { iso_rule_3 } \
         -location from \
         -within_hierarchy u_dig_top_pdmcu \
         -prefix ISO3_LOW_

#PD_HFADC
create_isolation_rule -name iso_rule_2 \
     -from { PD_HFADC } \
     -isolation_output low \
     -isolation_condition u_pmu_top/dig1_pm_if.iso_enable \
     -isolation_target from  \
   -exclude {}

update_isolation_rules -names { iso_rule_2 } \
     -location from \
         -within_hierarchy u_apb_peripheral_system/u_dig_adc/x_adc_hf \
     -prefix ISO2_

###########
## state retention rules
create_state_retention_rule -name ret_rule_1 \
     -domain PD_MCU \ => all flops in this domain are treated as retention flops except for flops in "exclude" modules below
     -restore_edge !u_pmu_top/dig0_pm_if.ret_enable \ => only 1 of save/restore needed
         -save_edge u_pmu_top/dig0_pm_if.ret_enable \ => NOTE: save is opposite polarity of restore
         -exclude u_dig_top_pdmcu/u_ahb_peripheral_system/u_flash_top/u_hardip ... \ => flops in these are excluded as retention
     -target_type flop

###########
##nominal condition
create_nominal_condition -name on \
     -voltage { 1.08 } \
     -ground_voltage { 0 }

create_nominal_condition -name off \
     -voltage { 0 } \
     -ground_voltage { 0 }

update_nominal_condition -name on -library_set QC_MAX_1.2V_INDUSTRIAL_PD_TOP_timing => This lib set defined above comprising of .lib for all cells
update_nominal_condition -name off -library_set QC_MAX_1.2V_INDUSTRIAL_PD_TOP_timing

##power modes
create_power_mode -name run \
     -default \
     -domain_conditions {  PD_TOP@on PD_MCU@on PD_HFADC@on }

create_power_mode -name sleep_hfadc_on \
     -domain_conditions {  PD_TOP@on PD_MCU@off PD_HFADC@on }

create_power_mode -name sleep_hfadc_off \
     -domain_conditions {  PD_TOP@on PD_MCU@off PD_HFADC@off }

## assertion controls
create_assertion_control -name ac1 -domains {PD_MCU} -type suspend

## This gets the cell to rerun "initial" block, when it powers up. This allows us to get init values of mem again.
set_sim_control -action power_up_replay \
         -targets { * } \
         -instances { \
            u_dig_top_wrapper/u_dig_top/u_efuse_wrap \
         } \
         -modules {
            ROM_INST \
         }

###############
##define lib sets
define_library_set -name QC_MAX_1.2V -lib {a_W_150.lib ... c.lib}
define_library_set -name QC_MIN_1.2V -lib {a_S_-40.lib ... c.lib}

update_nominal_condition -name on \
     -library_set QC_MAX_1.2V_INDUSTRIAL_timing

#include other tech cpf files
include "/db/.../CORE_RET.cpf" => CORE_RET.cpf has defines for state retention flops
i.e:  (similarly for all other retention flops)
define_state_retention_cell -cells { RET_CELL_X1 } -cell_type \
    CLK_HIGH -clock_pin CLK -save_function ~RETZ -power_switchable VDD -power \
    VDDC -ground VSS

include "./CPF/MY_RAM.cpf" => CPF files for RAM/ROM etc

end_design

 

Running Power Aware Sims in RTL:

To run power aware sims in irun, add these extra args:
irun ....
             -lps_cpf /db/dig_top_rtl_pasim.cpf \ => cpf file
                     -lps_pmode \
                     -lps_isoruleopt_warn \
                     -lps_isofilter_verbose \
                     -lps_logfile lps.log \
                     -lps_pa_model_on \
                     -lps_stime 1us \
                     -lps_verbose 3  \
                     -lps_iso_verbose \
             -lps_verify \ => to turn on asserts in low power mode

Details
Published: Thursday, 04 February 2021 01:29
Hits: 1271

Power Intent:

If you recall RTL coding in any HDL language, there is no way to model power connections in RTL. HDL langauges never had power definitions in them. Earlier in 1980's when HDL were being developed, all chips had single power, so there was no need to specify power connections at RTL level. These power connections to std cells were done in physical implementation phase, by the tools. It was very easy to do these, as power lines, VDD and VSS would just connect to power ports of std cells. The power grid for VDD, VSS would finally come to the pads of chip as ppower pins.

Earlier, power was not a concern, so power specific cmds in HDL were never considered. However, now power is a big concern, and a lot of effort goes into reducing power. This involves reducing lkg power of chip, by turning off portions of chip when not in use. Also, multiple voltage supply rails are being used, whose voltage range is dynamic. This asks for putting power definition in RTL to specify what logic is connected to what power supply. However, putting power connections in RTL reduces flexibility of RTL modeling, as it's supposed to focus more on functional aspect. So, standards were developed, which is a separate file with power intent of RTL coded in it, in a syntax called as power formats (PF). This PF file doesn't modify the RTL, but instead adds an abtract layer that defines how various code in RTL are connected to power supply. Simulation tools understand these PF, and simuate design with both RTL and PF in tandem. This is known as "power aware RTL sim" (PARTL Sim). These tools will thrown out an "x" from RTL code, when power supply to that piece of RTL code is OFF.  Thus it allows us to verify our design much before it goes thru physical implememtation. Also, Synthesis/Layout tools can also read this PF file and can know what piece of logic connects to what power supply. That keeps power supply connections easy and automated.

The netlist generated by synthesis/pnr tools can be non PG netlist (netlist which has no power ports for stdcells and modules), or PG netlist (one which has power ports VDD/VSS for stdcells and modules). We can specify what kind of netlist we want generated using options when writing netlist. When we had single power designs, PG netlists were not important as they all connected to single power supply, and didn't provide any extra info. However, now with advent of PF, we more commonly generate PG netlist, which shows power connections to each and every stdcell/macro. This allows us to run power aware simulations on gate level netlist (PAGLS sims). This extra sim allows us to find out if all power connections speciifed in PF file, were indeed done as intended. This sim doesn't need PF file, as all power connections are there in gate level netlist. 

 

Power Standards:

There are 2 PF standards in use today:

1. UPF (Unified Power format): The IEEE 1801 Unified Power Format (UPF) Standard establishes a set of commands used to specify the low-power design intent for electronic systems.

UPF manual can be downloaded from IEEE website. Std started developing in 2009. Current one is IEEE Std 1801-2017

See Design Compiler guide (Page 154) section 6-18 (specifying power intent) for details.

2. CPF: (Common Power format): This Format was introduced by Cadence, but shortly thereafter, UPF was proposed. Since UPF hasd backing of lot more companies, it was chosen as IEEE std, and CPF became less popular. The technical differences between the two formats are relatively minor. CPF is not really needed anymore as all tools support UPF now. I've a section on CPF, but it's for my reference only. You can omit it completely.

 

Terminology used in UPF/CPF:

Using UPF/CPF commands, you can specify the supply network, switches, isolation, retention, and other aspects relevant to power management of a chip design.

Power management (PM):  Power management enables a system to operate correctly in a given functional mode with the minimum power consumption. Implementation of pwr mgmt strategies require PM cells as level shifter, isolation, retention reg and repeaters to ensure that the design works correctly in the presence of diff pwr domains. PM cells may have single set of supply (i.e iso cell in destination PD), dual set of supply (i.e iso cell in source PD, level shifter, retention flops, pwr switch) or even more. Objects supplying pwr can be in various supply states, while objects consuming pwr can be in various power states. Supply state of supply port, supply net or supply set function is a combo of 2 values: state value (which may be OFF, UNDETERMINED, PARTIAL_ON and FULL_ON), and a voltage value (value in uV). Powr states are various legal states that objects can be in. These objects may be supply nets/ports/sets, PD, etc.

Below we briefly define various terms used in PM. We'll cover in more detail in UPF section. The terminology I've below is written for UPF, but applies to CPF as well.

1. Power domain:  It's defined group of elements in the logic hierarchy that share a common set of power supply needs. By default, all logic elements in a power domain use the same primary supply and primary ground, and may share other auxillary supplies such as isolation and retention supplies (explained later). A power domain may be single instance or collection of instances, powered by same supply. We define power domains in UPF to identify separate power regions in RTL. power domain identifies the uppermost inst of the domain. Every instance in design should be part of some power domain.

2. scope and extent: Each power domain has a scope and an extent. The scope is the level of logic hierarchy where the power domain exists. Scope in HDL refers to "region of HDL text where names may be defined".  Usually scope is module, submodule or blocks of statement, which can all be nested. Scope in UPF means the same. The extent is the set of logic elements that belong to the power domain and share the same power supply needs. In other words, the scope is the hierarchical level (instance of a module) where the power domain exists, whereas the extent is what all logic is contained within the power domain. So, with "set_scope" cmd, we specify which module of RTL the UPF file applies to. The scope in UPF is set to top module of RTL. If we want UPF file to be applied to some submodule in RTL, we have to set scope accordingly. Extent allows us to omit/include things within that scope that are prsent or absent in that power domain (i.e may be a set of logic within a submodule is supposed to be connected to some other power supply, in this case extent allows us to omit this from this power domain). Otherwise by default, power domain connects everything that is contained in that design hier to that supply to which that power domain is connected to.

Other way to define scope/extent is this: The instance in the logic hierarchy in which a power domain is defined is called the scope of the power domain. The set of instances that belong to a power domain are said to be the extent of that power domain. This distinction is important: while a given instance can be the scope of multiple power domains (i.e 1 power domain may be nested inside other power domain), it can be in the extent of one and only one power domain (since cell power suplly can only be connected to unique pwr supply, i.e VDD pin of cell can't be connected to 2 pwr supply pins). As a consequence of these definitions, all instances within the extent of a domain are necessarily within the scope of the domain or its descendants

3. nets and ports: Each scope or hierarchical level in the design has supply nets and supply ports. A supply net is a conductor that carries a supply voltage or ground throughout a given power domain. A supply port is a power supply connection point between two adjacent levels of the design hierarchy, between parent and child blocks of the hierarchy. We define supply nets and ports in UPF for power signals, even though these power signal nets/ports are absent in RTL. That is how UPF is able to define power intent of design. For macros or power management cells, these power ports may be specified in liberty or thru 'create_supply_port" upf cmds.

Supply net originates at a root supply driver, which can be an on-chip voltage regulator, an embedded power switch, a bias generator, or an off-chip supply source. One or more of these supply nets connect to a power switch, which has single output supply port. Supply network objects are created independent of power-domain definitions. This allows sharing of common components of the supply distribution network across multiple power domains.

4. Supply set: Related supply nets can be grouped into a supply set, with each supply net in the group providing one or more functions of the supply set. In other words, a supply set represents a collection of supply nets that provide a complete power source for one or more instances. Each supply set defines six standard functions: power, ground, pwell, nwell, deeppwell, and deepnwell. Each function represents a potential supply net connection to a corresponding portion of a transistor. Each function of a given supply set can be associated with a particular supply net that implements the function.

Mostly, power and ground are the only 2 supply nets that are needed (as pwell and nwell connections are tied internally to power/ground). Supply functions of a supply set, and the supply nets they represent, can be connected to instances in one of the following ways: explicitly, automatically, or implicitly. Connections are made downward, from ports or nets in the current scope to ports of descendant instances that are in the extent of the domain.

Supply sets may be primary, retention, isolation or level shifter supply sets, depending on what kind of cell they are meant for.

Supply Set Connections: Supply functions of a supply set, and the supply nets they represent, can be connected to instances in one of the following ways: explicitly, automatically, or implicitly. Connections are made downward, from ports or nets in the current scope to ports of descendant instances that are in the extent of the domain.

  1. explicit connection:
  2. automatic connection: In liberty file, each port has a pg_type as primary power, primary_ground, pwell, nwell, deeppwell, deepnwell. These are connected with matching function names in supply set
  3. Implicit connection: An implicit connection connects the required functions of a supply set to cell instances that do not have explicit supply ports.

5. Supply variation: Supply ports, supply nets, and supply set functions take on values that consist of a state and a voltage. Named port states (see 6.4) and named power states (see 6.5) can be defined to represent the nominal voltages that a supply object may carry. These nominal voltage values are used also for determining whether level-shifting is required (see 6.45). In an implementation, the actual voltage of an object may vary around the nominal values. There are several sources of such variation. One source of variation is the accuracy of the supply. Supply variation can be modeled in UPF using the set_variation command (see 6.53). Supply variation is applied to nominal voltages to derive variation ranges for those voltages. Supply variation ranges (see 4.5.7) are used when determining whether level-shifting is needed.

6. Power states: As explained above, power states represent various operational modes of the domain's supply set. As an ex, a power domain may have 3 states: RUNNING, SLEEP and SHUTDOWN. In RUNNING, all supply sets may be at optimal voltage, while in SLEEPING, they might be at reduced voltages. In SHUTDOWN, primary supply may be OFF, while retention and isolation supplies may be ON). A value of 0 or L in HDL is considered ON or FULL_ON, while a value of 1 or H in HDL is considered OFF. X or Z may be considered UNDETERMINED or PARTIAL_ON depending on settings.

7. power switch: A power switch (or simply switch) is a device that turns on and turns off power for a supply net. A switch has an input supply net, an output supply net that can be switched on or off, and at least one input signal to control switching.

Supply network objects (supply ports, supply nets, and switches) are created within the logic hierarchy to provide connection points for a root supply and to propagate the value of a root supply throughout a portion of the design.


8. level shifter: Where a logic signal leaves one power domain and enters another at a substantially different supply voltage, a level-shifter cell must be present to convert the signal from the voltage swing of the first domain to that of the second domain.

9. isolation cell (aka clamp cell): Where a logic signal leaves a power domain and enters a different power domain, an isolation cell must be present to generate a known logic value during shutdown. If the voltage levels of the two domains are substantially different, the interface cell must perform both level shifting when the domain is powered up and isolation when the domain is powered down. A cell that can perform both functions is called an enable level shifter. Tools can optimize away redundant insertion of iso cells (i.e when nets are tied to constant logic, etc)

Isolation may be inserted for an input or for an output of the power domain. It's placed at i/p so that values coming into the power domain are deterministic even when the driver is powered down. They are needed at o/p so that values coming out of this power domain and going into other domain are deterministic even when driver is powered down. If we think about it, we may infer that isolation cells may need to be provided at i/p ports only, since o/p of a port may fan out to different with different clamp value requirements, so providing iso cells at all i/p ports only may work out. However, if we don't provide iso cells at o/p, then the "unknown" values will be going thru nets to all other blocks. These nets will need repeaters to carry the signal, and unknown inputs may cause short circuit current thru repeaters. So, we provide iso cells at both i/p and o/p of all blocks. Isolation cell's power supply for i/p ports is from same PD supply which is consuming it (as isolation is relevant only when the supply for that PD is on). However, this may be an issue for o/p ports, as they will become floating if driven by same power supply. So, we prefer to drive o/p ports with always on power supply, so that we are guaranteed valid iso values all the time??

An isolation cell operates in two modes: normal mode, in which it acts like a buffer, and isolation mode, in which it clamps its output to a defined value. An isolation enable signal determines the operational mode of an isolation cell at any given time.

9. retention reg/flops and memories: In a power domain that has power switching, any registers that are to retain data during shutdown must be implemented as retention registers. A retention register has a separate, always-on supply net, sometimes called the backup supply, which keeps the data stable in while the primary supply of the domain is shut down. Retention capability can be implemented for both registers and memories.

There are 2 flavors of retention reg:

  1. Balloon-style retention: In a balloon-style retention register, the retained value is held in an additional latch, often called the balloon latch. In this case, the balloon element is not in the functional data-path of the register.Extra save/restore ports are needed to save or restore the values.
  2. Master/slave-alive retention: In a master/slave-alive retention register, the retained value is held in the master or slave latch. In this case, the retention element is in the functional data-path of the register. This style of registers does not have save/restore ports, but may specify a retention condition that could take the register in and out of retention (i.e when power supply turned on/off).

10. Repeaters: Required when distance b/w driver and receiver is large. These repeaters should be on appr power domain.

 

 

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