SPMI

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Last Updated: Wednesday, 03 December 2025 00:14

Published: Tuesday, 02 December 2025 22:30

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SPMI = System Power management Interface

SPMI bus protocol is defined by the MIPI alliance (version 2.0 released in 2012). It allows for communication b/w Power controllers (PC) on a chip (SoC = System on Chip) and a PMIC (Power management IC). This i/f is used to send cmds from master (which is the SoC) to slave (which is the PMIC) to ask the slave to change voltage on voltage lines. These voltage lines are driven by LDO or Switching regulators (i.e Buck Converters) on the PMIC, and drives power pins on the SoC.

DFVS (Dynamic Frequency and Voltage scaling): DVFS is a very comon technique used in SoC where voltage are frequency are changed according to the needs of the system to save power. SPMI protocol is used to drive this. This is the sequence => SoC writes to registers in PMIC, and if successful, PMIC changes voltages in response to cmds it received. Voltage may be changed in steps and in a particular order to ensure voltage levels are in compliance with what the SoC can tolerate. SoC gets the new voltage levels on it's power pins. At powerup, there is some default voltage that is driven by PMIC, and once SoC sends updated cmds, the voltages are adjusted accordingly by the PMIC, and driven to SoC.

SPMI protocol:

SPMI Protocol Basics (Rhode and Schwarz) => https://www.youtube.com/watch?v=kVuTSN6JwIQ

SPMI is a 2 wire interface, one clk and other data:

• SCLK: Unidirectional. driven by Master. Freq from 32 KHz to 24MHz
• SDATA: Bidirectional. can be driven by Master or Slave. 

Bus transactions start from bus being in Idle state: SCLK and SDATA being low. Then a cmd sequence starts. 4 parts to cmd seq:

1. SSC (seq start cond) => Here Data line (SDATA) is pulled high for 1 clk cycle and then oulled low for another clk cycle, while SCLK is still in Low state. This iis used by master or slave to indicate to the other side that cmd seq is starting. After the SSC. the bus owner starts the clock and frame transmission begins
2. Three different types of frame:
   1. Cmd frames: It is a 13 bit frame. 1st 4 bits are either slave addr (16 slaves possible) or master addr (1st 2 bits are 0, next 2 bits are master addr allowing for 4 masters). These addr are called as Identifiers. These addr are staic and defined by the manufacturer. If driven by Master, then 4 bit slave addr used to target the particular slave, while if used by slave, then 2 bit master addr used to target the particular master (in a multi master mode). Addr is followed by 8 bits of cmd which indicates the type of cmd (sleep, rd/wrt, etc). 8 bit cmd may contain some bits for addr too (depending on the cmd type). There's an additional parity bit for error checking. It's odd parity, meaning the total # of 1's should be odd. So, if the 12 bits are all 0s, then 13th parity bit should be 1 so that # of 1's is odd. 
      1. 4 tpes of SPMI cmds:
         1. State mgmt cmds: Used to change states of the slave. 4 states defined => Startup state, active state, sleep state and shutdown state. In this case, cmd of 8 bits is 0001_00XY, where XY are the 2 bits for the 4 states. Then a Parity bit is sent, followed by BP to xfer control to slave (see BP below). Slave then sends 1 bit ACK/NACK (see below) and then again a BP to xfwr control back to Master.
         2. Authentication cmds: These are used for device identification and IP mgmt. Floowing SSc and slave addr, 8 bit cmd of 0x14 identifies it as authentication cmd. Then 1st challenge frame is sent by master, to which the slave sents a Response frame. This continues for 4 such frames of challenge and response.Contents are deiced by manufacturer. A slave that doesn't support authentication, sends a "No response frame" which is all 0's (discussed below)
         3. Register access cmd: To read data from or wrt data to device. 
            1. Reg read: SSC followed by 4 bit slave addr, followed by 011 (3 bits to indicate rd cmd) and then 5 bit reg addr (32 reg possible). Then parity bit, then BP to xfer control to slave (see BP below), and then slave sends the 8 bit data from the reg, folowed by Parity bit, and then again a BP to xfwr control back to Master. Not sure if ACK/NACK is sent by the master to the slave after reading the reg bits?
            2. Reg write: Similar to reg rd, except that wrt data is also driven by the master. Then a BP, ACK/NACK and BP done (similar to rd reg case)
   2. Data/Address frames: This is a 9 bit frame, with an additional parity bit. It's odd parity, meaning the total # of 1 should be odd. So, if the 8 bits are all 0s, then 9th parity bit should be odd. We either provide addr of reg, or the data to write to the reg, or the data read from the reg is put on this line.
   3. No response frames: This is either a 13 bit (for cmd frame) or 9 bit (for data/Addr frame). The bits in here are all 0 (i.e SDATA is low). 
3. Bus Park (BP): This seq is used to release the data bus by the owner. This is needed since both slave and master can drive the bus. BP returns the bus to idle state as clk and data both go low. On rising edge of SCLk, SDATA is pulled low, and then SCLK goes low too. This allows another device to take control of the bus, in order to send a cmd or ack.
4. ACK/NACK: This is 1 bit to indicate an ACK (a 1) or NACK (a 0) for cmd and data/addr frames. After a frame transmission, 1 bit BP is sent to xfer control of SDATA to the receiving device. Master still controls the SCLK line and drives next clk cycle on which the receiving device sends an ACK/NACK. After this a second BP is performed by the receiving device to release the SDATA line